Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
Topic / Topic starter Post date Replies Last Post
Normal topic TSX conflict aborts for single threaded applications
by futureishere
Mon, 08/26/2013 - 08:03 6
by futureishere
Thu, 09/05/2013 - 07:13
Normal topic Efficiently multiplying an array/vector by a constant with AVX
by dehvidc1
Tue, 05/03/2016 - 21:20 1
by Tim P.
Wed, 05/04/2016 - 04:16
Normal topic Weird Derived Cache Latency
by Min X.
Mon, 03/27/2017 - 20:15 1
by Thomas Willhalm...
Tue, 03/28/2017 - 02:16
Normal topic pmu-tools for Intel PMU features on top of linux perf
by Andreas Kleen (...
Sun, 08/03/2014 - 12:39 1
by Thomas Willhalm...
Sun, 08/03/2014 - 13:18
Normal topic isCoreOnline will always return false if /proc/cpuinfo doesn't print "physical id" and / or "core id"
by Valentin Bondzio
Mon, 06/22/2015 - 01:41 10
by Valentin Bondzio
Tue, 06/23/2015 - 05:36
Normal topic 4th gen (Haswell) undocumented events?
by nsmeds
Thu, 06/27/2013 - 03:37 12
by McCalpin, John
Wed, 08/14/2013 - 15:29
Normal topic help for tuning application's startup
by jinjunsheng
Tue, 10/18/2011 - 03:45 5
by iliyapolak
Thu, 02/14/2013 - 22:55
Normal topic Cache Coherence in Ivy Bridge
by Divino C.
Thu, 10/24/2013 - 13:15 10
by iliyapolak
Mon, 10/28/2013 - 00:22
Normal topic Tracking what prevents the processor from entering deeper PCStates
by Victor P.
Mon, 08/15/2016 - 10:43 0
by Victor P.
Mon, 08/15/2016 - 10:43
Normal topic OFFCORE events for CODE/DATA traffic measurements on Sandy Bridge
by Alexander Alexeev
Thu, 11/06/2014 - 13:57 0
by Alexander Alexeev
Thu, 11/06/2014 - 13:57
Normal topic Inconsistent L2 HW Prefetch behavior on Haswell
by McCalpin, John
Tue, 09/08/2015 - 14:00 3
by McCalpin, John
Fri, 09/11/2015 - 13:07
Normal topic Why is my application not able to reach core i7 920 peak FP performance
by Dan Leakin
Wed, 02/29/2012 - 06:35 4
by Patrick Fay (Intel)
Wed, 02/29/2012 - 06:35
Normal topic PCM Westmere support
by Mark Smith
Wed, 02/26/2014 - 18:46 0
by Mark Smith
Wed, 02/26/2014 - 18:46
Normal topic How to measure the performance on multi-programmed workloads.
by Daejin J.
Tue, 10/25/2016 - 06:36 0
by Daejin J.
Tue, 10/25/2016 - 06:36
Normal topic Xeon E5 26xx v3 energy monitor error
by Roberto R.
Fri, 02/27/2015 - 01:58 7
by Roberto R.
Mon, 03/02/2015 - 08:40
Normal topic Intel PCM APIs Question
by Spivoler
Mon, 12/07/2015 - 02:00 2
by Spivoler
Thu, 12/10/2015 - 13:51
Normal topic Disabling cache coherancy
by balu.r.0212
Mon, 05/14/2012 - 04:00 2
by balu.r.0212
Wed, 05/16/2012 - 04:28
Normal topic PCU event FREQ_TRANS_CYCLES not changing
by Black.S
Mon, 06/30/2014 - 10:16 12
by Black.S
Mon, 07/14/2014 - 10:24
Normal topic Core i5 2nd Generation (Sandy Bridge) - Disable only cache L2/L3
by Ciro V.
Sun, 09/23/2012 - 02:56 0
by Ciro V.
Sun, 09/23/2012 - 02:56
Normal topic Configure and read iMC Performance Counters with Haswell E5 and missing /sys/devices/ export
by Stephan W.
Thu, 01/19/2017 - 11:00 5
by McCalpin, John
Thu, 02/09/2017 - 09:46
Normal topic -g option slows down execution
by Frederico C.
Wed, 05/06/2015 - 10:19 1
by Tim P.
Wed, 05/06/2015 - 15:50
Normal topic Disabling RAPL
by Mustafa K.
Thu, 02/25/2016 - 12:38 1
by McCalpin, John
Fri, 02/26/2016 - 09:10
Normal topic Attention: Windows Update problems on Windows XP 32-bit OS
by Sergey Kostrov
Tue, 07/17/2012 - 21:52 6
by iliyapolak
Thu, 07/19/2012 - 14:01
Normal topic Minimum Redirect Latency from IF/DE and Uop$
by perfwise
Tue, 02/12/2013 - 06:09 9
by iliyapolak
Thu, 02/21/2013 - 21:51
Normal topic Modifying QPI Routing Table Array.
by wonjun s.
Thu, 05/09/2013 - 11:31 1
by Patrick Fay (Intel)
Thu, 05/09/2013 - 12:54
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For more complete information about compiler optimizations, see our Optimization Notice.