Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Normal topic Question about Core Specificity Encoding option for reading cpu performace counters
by Hamid Reza K.
Wed, 04/01/2015 - 10:43 1
by John McCalpin
Wed, 04/01/2015 - 11:13
Hot topic Can't use PCM
by korso
Thu, 06/14/2012 - 08:17 28
by Roman Dementiev...
Mon, 09/30/2013 - 01:21
Normal topic Streaming stores and split cache line loads on Sandy Bridge-EP and Ivy Bridge-EP
by Johannes Hofmann
Mon, 02/08/2016 - 05:05 4
by John McCalpin
Wed, 02/10/2016 - 13:47
Normal topic Sandybridge time critical pipeline stage
by gortipavan
Thu, 08/23/2012 - 12:42 1
by iliyapolak
Tue, 02/12/2013 - 00:45
Normal topic pcm tools - does pcm-memory.x show memory bandwidth to the core(s), or also to the PCIe devices?
by Adrian C.
Tue, 09/03/2013 - 12:09 10
by iliyapolak
Sun, 09/22/2013 - 00:43
Normal topic How to build WinMsrDriver of Intel PCM (version 2.11) with Visual Studio 2015 under Windows 10?
by Jeremy W.
Sat, 08/27/2016 - 11:50 0
by Jeremy W.
Sat, 08/27/2016 - 11:50
Normal topic Configuring cache partitioning; how?
by Tim Day
Thu, 07/31/2014 - 10:03 3
by John McCalpin
Thu, 07/31/2014 - 16:46
Normal topic Setting MSR 0x1AD (turbo ratio limits) has no effect on Sandy Bridge
by khenglish
Tue, 09/06/2011 - 09:32 4
by terabytes
Sun, 01/01/2012 - 23:40
Normal topic Intel PCM- Unsupported Processor Model error (Intel(R) Xeon(R) CPU E7-4860 v2 @ 2.60GHz (62))
by Mahwish A.
Mon, 06/15/2015 - 08:04 9
by Roman Dementiev...
Mon, 06/22/2015 - 03:20
Hot topic TSC Synchronization Across Cores
by Samuel M.
Tue, 04/16/2013 - 20:00 18
by Sergey Kostrov
Fri, 04/26/2013 - 20:49
Normal topic Have a beeping problem with new ram memory.
by pinger d.
Sun, 03/30/2014 - 13:19 4
by iliyapolak
Mon, 03/31/2014 - 06:22
Normal topic Inline assembly to generate most heat on SB-E
by CommanderLake
Tue, 02/24/2015 - 09:59 14
by iliyapolak
Sat, 02/28/2015 - 22:58
Normal topic Perfomance monitoring issues
by heinerj
Fri, 04/20/2012 - 08:21 1
by Patrick Fay (Intel)
Thu, 07/26/2012 - 06:17
Normal topic Finding arithmetic intensity of application
by Ashutosh L.
Wed, 12/02/2015 - 02:44 13
by John McCalpin
Tue, 12/22/2015 - 08:14
Normal topic Flushing Code Coverage data to disk
by Roberto D.
Tue, 08/13/2013 - 08:43 2
by Roberto D.
Tue, 08/13/2013 - 09:05
Normal topic can you give PCIe reads/writes priority over reads/writes from the cores?
by unclejoe
Wed, 06/08/2016 - 17:56 0
by unclejoe
Wed, 06/08/2016 - 17:56
Normal topic Cache Enabled/Disabled?
by heinerj
Fri, 04/27/2012 - 08:40 4
by rahim25
Thu, 05/10/2012 - 10:40
Normal topic How can i building Intel PCM without NMI watchdog check?
by Wenqin C.
Fri, 12/11/2015 - 01:43 3
by Wenqin C.
Sun, 12/13/2015 - 03:51
Hot topic Is it possible to access RAM directly while the memory is cached?
by le g.
Tue, 08/20/2013 - 05:51 17
by le g.
Tue, 09/03/2013 - 02:12
Normal topic Attributing lost cycles to cache misses and mis predictsIdentifying if data locality and branch mis predicts
by Hayden L.
Tue, 06/21/2016 - 11:26 2
by Thomas R.
Wed, 06/22/2016 - 03:25
Normal topic BACLEAR and BPUCLEAR
by perfwise
Thu, 02/21/2013 - 12:04 0
by perfwise
Thu, 02/21/2013 - 12:04
Normal topic Clarification about data source encoding for PEBS Load latency samples
by Manuel S.
Mon, 02/03/2014 - 01:32 0
by Manuel S.
Mon, 02/03/2014 - 01:32
Normal topic Per core energy analysis
by ARNAB R.
Sat, 12/20/2014 - 23:49 2
by iliyapolak
Tue, 12/23/2014 - 10:37
Normal topic Core Speed Issue?
by thebanker101
Sun, 03/18/2012 - 20:03 2
by revogirl
Sun, 03/18/2012 - 20:03
Normal topic Is L2 Cache Inclusive to L1 Instruction Cache (micro-op cache) in Intel Sandy Bridge?
by Steven P.
Fri, 10/09/2015 - 17:16 1
by Tim P.
Sat, 10/10/2015 - 07:00
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For more complete information about compiler optimizations, see our Optimization Notice.