Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
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Topic / Topic starter Post date Repliessort descending Last Post
Normal topic Sandybridge supports 1G byte page?
by Ray Song
Sun, 07/31/2011 - 21:11 2
by Ray Song
Wed, 08/03/2011 - 22:29
Normal topic Linux kernel for xeon E5-2665 machine
by Rakhi H.
Thu, 09/12/2013 - 09:29 2
by iliyapolak
Wed, 09/18/2013 - 08:04
Normal topic Sandy Bridge L2 Writeback to L3, PMC 0xF2
by perfwise
Thu, 09/15/2011 - 15:48 2
by perfwise
Thu, 09/15/2011 - 15:48
Normal topic About architectural and nonarchitectural performance-monitoring events
by Chenjie Y.
Tue, 08/20/2013 - 07:19 2
by Chenjie Y.
Wed, 08/21/2013 - 03:36
Normal topic Memory type aliasing
by developer
Wed, 02/05/2014 - 03:21 2
by McCalpin, John
Wed, 02/05/2014 - 14:08
Normal topic Measure uncore frequency on my Skylake CPU
by Travis D.
Wed, 02/01/2017 - 14:10 2
by Thomas R.
Mon, 02/13/2017 - 05:23
Normal topic memory bandwidth on core i3 (Westmere/Clarkdale)
by Aleksandr B.
Thu, 10/15/2015 - 02:21 2
by Aleksandr B.
Wed, 11/11/2015 - 23:14
Normal topic Intel Performance Counter Monitor (Intel PCM) 2.6 released
by Thomas Willhalm...
Thu, 11/07/2013 - 05:09 2
by Jaeyoon C.
Thu, 11/07/2013 - 22:06
Normal topic Running results are different for an application from compiling -O0 option and -O3 option
by Lyndon L.
Wed, 09/18/2013 - 14:56 2
by Lyndon L.
Wed, 09/18/2013 - 18:56
Normal topic [PCM] Processor Counter Monitor replaces Intel Performance Counter Monitor
by Thomas Willhalm...
Thu, 01/05/2017 - 11:59 2
by Thomas Willhalm...
Thu, 01/19/2017 - 08:40
Normal topic PCM uses events and masks that I couldn't find in specs. Then where?
by Alexander Alexeev
Fri, 04/19/2013 - 07:23 2
by Patrick Fay (Intel)
Mon, 04/22/2013 - 15:00
Normal topic some question about QPI
by Yinchao Z.
Wed, 03/30/2016 - 19:06 2
by McCalpin, John
Tue, 04/05/2016 - 12:16
Normal topic Intel HD 3000 - gaming
by arnsa
Thu, 07/12/2012 - 08:05 2
by iliyapolak
Thu, 07/12/2012 - 10:10
Normal topic Programming PEBS Counters
by Arnabjyoti K.
Sat, 05/27/2017 - 09:17 2
by Arnabjyoti K.
Thu, 06/01/2017 - 14:13
Normal topic Intel® 5 Series HM55 chipset Power-Up questions
by Lior M.
Thu, 10/02/2014 - 00:42 2
by Lior M.
Sun, 10/05/2014 - 01:10
Normal topic 0 L3 Cache Misses reported
by (name withheld)
Tue, 06/13/2017 - 21:00 2
by Roman Dementiev...
Mon, 06/19/2017 - 04:46
Normal topic Trying to make sense of L1D (0x51), L2_RQSTS(0x24) and OFFCORE_REQUESTS (0xB0)
by perfwise
Tue, 12/06/2011 - 19:35 2
by Patrick Fay (Intel)
Tue, 12/20/2011 - 08:07
Normal topic Why QPI traffic captured by PCM is larger than bandwith of QPI port?
by li y.
Mon, 10/10/2016 - 02:34 2
by li y.
Wed, 10/12/2016 - 23:33
Normal topic Overwrite Locked Bits in a Memory Controller
by Saptarshi S.
Mon, 11/18/2013 - 16:34 2
by Patrick Fay (Intel)
Fri, 01/24/2014 - 07:53
Normal topic Intel HD4000 OpenCL code
by Mikhail Smirnov
Mon, 08/20/2012 - 06:51 2
by Mikhail Smirnov
Tue, 08/21/2012 - 00:30
Normal topic HOW to get the L1,L2 Cache Miss of an intel i5 Sandy Bridge
by eandy
Thu, 01/26/2012 - 11:21 2
by Shannon Cepeda ...
Thu, 01/26/2012 - 11:30
Normal topic Confusing hardware counters
by Bo W.
Thu, 10/20/2016 - 00:50 2
by Bo W.
Fri, 10/21/2016 - 12:54
Normal topic Measuring memory bandwidth through IntelPerformanceCounterMonitorV2.8
by Jeongseob A.
Wed, 04/29/2015 - 23:21 2
by Jeongseob A.
Thu, 04/30/2015 - 07:54
Normal topic Does disabling H/W prefetching affect prefetch/prefetchw instructions?
by Ming-Wei S.
Sun, 04/23/2017 - 15:19 2
by Tim P.
Wed, 04/26/2017 - 10:09
Normal topic CoreFreq
by CyrIng
Sat, 10/03/2015 - 01:22 2
by CyrIng
Sun, 07/09/2017 - 22:13
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For more complete information about compiler optimizations, see our Optimization Notice.