Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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This is a peer forum for developers using Intel® technology. Response times vary depending on the complexity of your issue.
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	Topic / Topic starter	Post date	Replies	Last Post
Normal topic	Problem when using profile-guided optimization by morfast	Tue, 07/03/2012 - 06:25	2	by morfast Thu, 07/05/2012 - 06:05
Normal topic	Intel® VTune™ Amplifier XE for Linux by Ramagounder t.	Wed, 04/16/2014 - 05:29	2	by Tim P. Wed, 04/16/2014 - 07:03
Normal topic	performance benefit in using large pages by Chris A.	Wed, 02/17/2016 - 02:43	2	by McCalpin, John Wed, 02/17/2016 - 08:58
Normal topic	Core Speed Issue? by thebanker101	Sun, 03/18/2012 - 20:03	2	by revogirl Sun, 03/18/2012 - 20:03
Normal topic	I need a document to describe vtune Events for Sandy Bridge by Allam F.	Fri, 10/11/2013 - 16:27	2	by Allam F. Sat, 10/12/2013 - 14:24
Normal topic	Arbitrary uncore event collection by Alexander Alexeev	Mon, 11/10/2014 - 11:22	2	by Roman Dementiev... Tue, 12/23/2014 - 06:42
Normal topic	Core i5-4300u thernal throttling stuck by Matt V.	Tue, 09/22/2015 - 19:59	2	by Matt V. Fri, 09/25/2015 - 13:01
Normal topic	What is the replacement policy of L2 and L3 on BroadWell CPU? by Zeke W.	Thu, 12/14/2017 - 01:15	2	by Travis D. Mon, 12/18/2017 - 22:11
Normal topic	TOR_INSERTS. MISS_OPCODE count is bigger than OPCODE. It is unexpected. by Alexander Alexeev	Thu, 08/29/2013 - 05:03	2	by Alexander Alexeev Thu, 08/29/2013 - 13:07
Normal topic	QPI Link Layer Packet Matching Reference "Gen By" by Paul C.	Thu, 07/30/2015 - 09:07	2	by Paul C. Fri, 07/31/2015 - 03:25
Normal topic	i5 Haswell power limitting registers by Martin D.	Sat, 01/03/2015 - 12:11	2	by iliyapolak Wed, 03/25/2015 - 10:44
Normal topic	Bug in PCM CSV formatting by Saliya E.	Fri, 10/16/2015 - 13:12	2	by Ameen A. Sun, 12/13/2015 - 23:46
Normal topic	What's CPU cache pipelining and how to use it ?? by Arthur V. Ratz	Sat, 09/30/2017 - 03:06	2	by Arthur V. Ratz Sun, 10/22/2017 - 04:22
Normal topic	Nehalem Prefetcher by heinerj	Fri, 06/22/2012 - 12:00	2	by heinerj Mon, 06/25/2012 - 09:44
Normal topic	SDM clarification needed - which tables (19-3 , 19-4, 19-9, 19-10, 19-11) apply to 06_3C processors? by Jason V.	Wed, 02/07/2018 - 07:21	2	by McCalpin, John Thu, 02/08/2018 - 11:26
Normal topic	Intel Performance Counter(pcm): Total QPI incoming data traffic ? by Prabhu T.	Thu, 11/15/2012 - 23:07	2	by Roman Dementiev... Fri, 11/16/2012 - 10:31
Normal topic	";" is missing in CSV output of pcm.x by Hidekatsu Imura	Thu, 02/12/2015 - 02:44	2	by Otto Bruggeman ... Thu, 02/12/2015 - 04:35
Normal topic	PCIe NUMA Affinity on Haswell & Ivy Bridge by John S.	Wed, 04/22/2015 - 20:18	2	by McCalpin, John Thu, 04/23/2015 - 12:17
Normal topic	How to run the Intel MLC by Wenxu Zheng	Sat, 03/10/2018 - 19:56	2	by McCalpin, John Mon, 03/12/2018 - 10:35
Normal topic	Is there any events for monitoring SIMD integer operations in E5 chip by Chenjie Y.	Fri, 08/23/2013 - 05:01	2	by Chenjie Y. Mon, 08/26/2013 - 01:56
Normal topic	Access to Processor Counter Monitor has denied by Matias C.	Thu, 04/20/2017 - 05:18	2	by gaston-hillar Thu, 04/20/2017 - 20:46
Normal topic	Monitor whether PCI bus is 33MHz or 66MHz by christian f.	Wed, 03/04/2015 - 19:32	2	by Patrick Fay (Intel) Fri, 03/06/2015 - 07:27
Normal topic	Is underclock harmful to the microprocessor? by alfa_one	Thu, 08/18/2011 - 13:49	2	by alfa_one Wed, 08/24/2011 - 12:20
Normal topic	Maximum size of the PEBS buffer by Arnabjyoti K.	Wed, 06/07/2017 - 08:57	2	by Arnabjyoti K. Mon, 06/19/2017 - 09:59
Normal topic	Q on TLB, Cache and Memory Timings by Jonathon D.	Fri, 10/23/2015 - 18:03	2	by McCalpin, John Mon, 10/26/2015 - 08:20

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For more complete information about compiler optimizations, see our Optimization Notice.

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