Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
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Topic / Topic startersort descending Post date Replies Last Post
Normal topic Collect TOR_INSERTS.OPCODE for two opcodes simultaneously
by Alexander Alexeev
Thu, 05/30/2013 - 02:24 2
by Roman Dementiev...
Fri, 06/07/2013 - 01:14
Normal topic Collecting raw PEBS dump on Linux
by arkaprava.basu
Mon, 09/03/2012 - 09:51 1
by Roman Dementiev...
Wed, 09/12/2012 - 01:16
Normal topic Comparing compilers
by magicfoot
Wed, 01/18/2012 - 05:05 14
by Tim P.
Fri, 02/03/2012 - 07:35
Normal topic Comparing scalar, SSE and AVX....poor performances ??
by Joaquin Tarraga
Wed, 06/06/2012 - 02:23 5
by Joaquin Tarraga
Thu, 06/07/2012 - 00:31
Normal topic Compiling with O3 giving segmentation fault
by Ashutosh L.
Wed, 03/29/2017 - 23:38 0
by Ashutosh L.
Wed, 03/29/2017 - 23:38
Hot topic Concerns on using AVX double floating point instructions for integer data
by cagribal
Thu, 12/13/2012 - 05:29 37
by Sergey Kostrov
Sun, 12/16/2012 - 12:04
Normal topic Concurrency support of CLFLUSH
by Steven H.
Mon, 02/06/2017 - 15:30 1
by McCalpin, John
Tue, 02/07/2017 - 13:24
Normal topic Configure and read iMC Performance Counters with Haswell E5 and missing /sys/devices/ export
by Stephan W.
Thu, 01/19/2017 - 11:00 5
by McCalpin, John
Thu, 02/09/2017 - 09:46
Normal topic configuring "unganged memory" in sandybridge
by balu.r.0212
Mon, 05/14/2012 - 03:58 4
by joe-griffin
Tue, 05/15/2012 - 06:54
Normal topic Configuring cache partitioning; how?
by Tim Day
Thu, 07/31/2014 - 10:03 3
by McCalpin, John
Thu, 07/31/2014 - 16:46
Normal topic Configuring Intel RAPL power limits
by Rajiv N.
Wed, 08/14/2013 - 04:06 3
by Patrick Fay (Intel)
Wed, 08/14/2013 - 08:13
Hot topic Configuring RAPL limits in Sandy Bridge Xeon processors
by Nobin M.
Thu, 04/18/2013 - 16:49 27
by Vasileios T.
Mon, 06/02/2014 - 09:54
Normal topic Confusing hardware counters
by Bo W.
Thu, 10/20/2016 - 00:50 2
by Bo W.
Fri, 10/21/2016 - 12:54
Normal topic Contradiction in manual for PCIe read combining
by Anuj K.
Thu, 08/27/2015 - 04:35 3
by McCalpin, John
Thu, 08/27/2015 - 19:41
Normal topic Convert IPv4 strings to 32-bit integers using SSE instructions
by Adrien Guinet
Fri, 05/16/2014 - 03:18 1
by iliyapolak
Fri, 05/16/2014 - 04:01
Normal topic Core i5 2nd Generation (Sandy Bridge) - Disable only cache L2/L3
by Ciro V.
Sun, 09/23/2012 - 02:56 0
by Ciro V.
Sun, 09/23/2012 - 02:56
Normal topic Core i5-4300u thernal throttling stuck
by Matt V.
Tue, 09/22/2015 - 19:59 2
by Matt V.
Fri, 09/25/2015 - 13:01
Normal topic Core Speed Issue?
by thebanker101
Sun, 03/18/2012 - 20:03 2
by revogirl
Sun, 03/18/2012 - 20:03
Normal topic CoreFreq
by CyrIng
Sat, 10/03/2015 - 01:22 2
by CyrIng
Sun, 07/09/2017 - 22:13
Normal topic Counting bus lock cycles on Skylake
by Arthur P.
Tue, 10/11/2016 - 03:16 1
by Thomas R.
Thu, 10/13/2016 - 06:44
Normal topic Counting Cache miss
by Ajit S.
Mon, 05/01/2017 - 23:55 4
by Travis D.
Wed, 05/10/2017 - 16:37
Normal topic Counting CPU cycles of a process with PMC0 counter
by Anubhav S.
Wed, 04/13/2016 - 05:15 0
by Anubhav S.
Wed, 04/13/2016 - 05:15
Normal topic counting flops (SIMD)
by José Luis G.
Fri, 01/10/2014 - 17:15 8
by McCalpin, John
Wed, 01/15/2014 - 12:48
Normal topic counting memory stall on Sandy Bridge
by liu x.
Mon, 05/05/2014 - 21:56 7
by McCalpin, John
Mon, 02/01/2016 - 09:07
Normal topic Counting MFENCE events with performance counters
by Tim M.
Fri, 10/31/2014 - 06:53 3
by Roman Dementiev...
Wed, 11/26/2014 - 05:12
New posts
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Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.