Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic starter Post date Replies Last Post
Normal topic intel extreme tuning utility error 1935
by Dale R.
Fri, 05/20/2016 - 10:12 0
by Dale R.
Fri, 05/20/2016 - 10:12
Normal topic Sandybridge supports 1G byte page?
by Ray Song
Sun, 07/31/2011 - 21:11 2
by Ray Song
Wed, 08/03/2011 - 22:29
Normal topic [PCM] Adding extra events "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM" and "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM"
by Ron C.
Wed, 10/09/2013 - 14:22 11
by Roman Dementiev...
Tue, 10/22/2013 - 04:28
Normal topic IntelPWMControl
by Vasya P.
Fri, 02/06/2015 - 06:18 12
by Lorenzo E.
Mon, 08/01/2016 - 04:13
Normal topic DRAM_DATA_READS/DRAM_DATA_WRITES
by James M.
Fri, 01/22/2016 - 18:40 4
by John McCalpin
Fri, 02/05/2016 - 08:32
Normal topic Understanding hardware performance counter event for STLB flush
by arkaprava.basu
Sun, 01/06/2013 - 11:06 10
by iliyapolak
Mon, 01/21/2013 - 09:18
Normal topic Caching H/W of Address Translation Structures on Intel64 Architectures
by drMikeT
Wed, 04/04/2012 - 12:06 8
by drMikeT
Tue, 08/04/2015 - 10:53
Normal topic Intel PCM - Can not access CPUs Model Specific Registers MSR
by Mahieddine D.
Wed, 05/28/2014 - 08:52 7
by Patrick Fay (Intel)
Thu, 05/28/2015 - 06:19
Normal topic jobs in lsf fails with more than 127 nodes
by Jose Gordillo
Wed, 06/10/2015 - 13:27 2
by Jose Gordillo
Tue, 06/23/2015 - 11:30
Normal topic Value of "IA32_VMX_MISC" MSR
by michael a.
Mon, 04/11/2016 - 04:01 0
by michael a.
Mon, 04/11/2016 - 04:01
Normal topic How can we know two PMU events are contradicting with each other or not?
by Hao Shen
Sun, 07/07/2013 - 12:55 7
by Hao Shen
Tue, 07/09/2013 - 07:52
Normal topic Some events missing in the manual is not necessarily inexistent!
by Chenjie Y.
Mon, 08/26/2013 - 12:33 1
by Patrick Fay (Intel)
Tue, 08/27/2013 - 09:09
Normal topic Are CYCLE_ACTIVITY.STALLS_LDM_PENDING and CYCLE_ACTIVITY.CYCLES_LDM_PENDING available on Sandy Bridge?
by Alexander Alexeev
Sat, 11/08/2014 - 13:52 2
by John McCalpin
Mon, 11/10/2014 - 08:09
Normal topic Cache misses for sequential vs. random access patterns
by Danilcha
Thu, 06/11/2015 - 10:35 6
by Danilcha
Tue, 07/07/2015 - 08:30
Normal topic MEM_UNCORE_RETIRED.OTHER_LLC_MISS performance event for Westmere
by Nikolay S.
Thu, 04/14/2016 - 13:59 1
by Nikolay S.
Thu, 04/14/2016 - 17:44
Normal topic Where I can get docs for CPUID and CPUID-like assembly registers ?
by bp
Thu, 07/25/2013 - 01:18 11
by iliyapolak
Fri, 07/26/2013 - 03:14
Normal topic PMU Events for Ivy Bridge
by Divino C.
Mon, 09/02/2013 - 14:25 4
by Divino C.
Tue, 09/03/2013 - 10:54
Normal topic Why UOPS_RETIRED.ALL greater than UOPS_RETIRED.RETIRE_SLOTS
by Alexander Alexeev
Tue, 11/18/2014 - 08:29 0
by Alexander Alexeev
Tue, 11/18/2014 - 08:29
Hot topic temporary pcie bandwidth drops on Haswell-v3
by Friedhelm S.
Tue, 11/24/2015 - 04:34 20
by John McCalpin
Wed, 09/07/2016 - 07:44
Normal topic Performance Monitoring Event tables
by Michael G.
Sat, 10/20/2012 - 14:50 1
by Shih Kuo (Intel)
Mon, 11/12/2012 - 16:27
Normal topic Intel PCM - Is there mistake on atom?
by GHui
Mon, 02/13/2012 - 19:17 3
by Roman Dementiev...
Thu, 03/22/2012 - 05:26
Normal topic Timely interaction of performance counters
by Olaf Krzikalla
Fri, 03/21/2014 - 06:59 8
by iliyapolak
Mon, 03/24/2014 - 10:41
Normal topic Why is an E5 1650v3 slower than an i5 4570S ??
by Marcus K.
Thu, 05/28/2015 - 09:51 8
by Tim P.
Sat, 05/30/2015 - 10:44
Normal topic Xeon E5 Family : Integrated Memory Controller
by Saptarshi S.
Wed, 05/29/2013 - 19:12 3
by John McCalpin
Thu, 05/30/2013 - 08:27
Normal topic Memory store retirenment
by Wang Jaff
Sun, 07/15/2012 - 09:28 6
by Hussam Mousa (Intel)
Mon, 08/13/2012 - 09:04
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For more complete information about compiler optimizations, see our Optimization Notice.