Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
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Topic / Topic starter Post date Replies Last Post
Normal topic Write Combine and non-temporal store's effect on IMC uncore events in Haswel-EX
by wang c.
Thu, 04/14/2016 - 07:12 9
by wang c.
Thu, 06/23/2016 - 08:23
Normal topic Counting number of uops
by Ayaz A.
Wed, 02/22/2017 - 10:19 3
by McCalpin, John
Fri, 02/24/2017 - 08:51
Normal topic The event CYCLE_ACTIVITY.STALLS_LDM_PENDING and CYCLE_ACTIVITY.STALLS_L1D_PENDING
by Yanjing Z.
Sat, 06/29/2013 - 07:40 1
by iliyapolak
Mon, 07/01/2013 - 10:09
Normal topic How to find out whether the last-level cache is shared between CPU and GPU?
by Bo W.
Mon, 10/20/2014 - 23:09 3
by iliyapolak
Tue, 10/21/2014 - 07:42
Normal topic Intel Performance Counter Monitor (Intel PCM) 2.9 released
by Thomas Willhalm...
Mon, 08/17/2015 - 08:32 3
by Carlos V. (Intel)
Fri, 12/04/2015 - 09:47
Normal topic Monitoring C1 and C1E core c-state
by Daniele C.
Wed, 07/20/2016 - 05:29 1
by McCalpin, John
Wed, 07/20/2016 - 06:53
Normal topic CR0 register, CD bit
by Urs M.
Wed, 06/28/2017 - 08:56 2
by Urs M.
Wed, 07/05/2017 - 09:45
Normal topic not counted when trying PEBS with perf
by Zhu G.
Sat, 02/07/2015 - 07:31 3
by Patrick Fay (Intel)
Sat, 04/25/2015 - 07:24
Normal topic Skylake cache latencies slower than Haswell?
by T C
Thu, 11/12/2015 - 16:13 1
by McCalpin, John
Sat, 11/14/2015 - 09:33
Normal topic Cache and AVX
by Gil S.
Sat, 10/15/2016 - 09:42 3
by Gil S.
Wed, 10/19/2016 - 10:24
Normal topic What is the problem that cause deadlock when I'm using LOCK# prefix inside PMI handler??
by Kelvin C.
Thu, 11/02/2017 - 02:12 0
by Kelvin C.
Thu, 11/02/2017 - 02:12
Normal topic Package Power of Intel SB
by Fabian Oboril
Sun, 11/13/2011 - 04:30 2
by Patrick Fay (Intel)
Fri, 11/18/2011 - 06:07
Normal topic Power implications of disabling USB
by Thomas Willhalm...
Mon, 08/26/2013 - 11:20 1
by Patrick Fay (Intel)
Mon, 08/26/2013 - 12:17
Normal topic write only memory bandwidth
by zachary w.
Thu, 09/27/2012 - 23:38 10
by McCalpin, John
Wed, 10/17/2012 - 11:08
Normal topic Ideal vectorization speed-up with SSE2 and MIC512 - not AVX?
by CK
Thu, 04/09/2015 - 07:48 4
by CK
Fri, 04/10/2015 - 02:31
Normal topic IMC and remote memory nodes
by Babis C.
Tue, 02/16/2016 - 03:20 4
by Babis C.
Tue, 02/16/2016 - 13:42
Normal topic TSCs per logical processor? Per socket?
by Corey R.
Thu, 12/22/2016 - 01:54 6
by Corey R.
Sun, 12/25/2016 - 21:57
Normal topic How does out-of-order execution cause PMI skid ??
by Kelvin C.
Thu, 03/01/2018 - 00:44 3
by McCalpin, John
Mon, 03/05/2018 - 08:46
Normal topic TLB misses
by cagribal
Wed, 03/07/2012 - 03:30 3
by Patrick Fay (Intel)
Wed, 03/07/2012 - 03:30
Normal topic [BUG][AVX] Invalid code generation using _mm256_unpacklo_pd and _mm256_permute2f128_pd
This topic has been moved to "Intel® C++ Compiler" (View topic)
Normal topic Performance Counters on SandyBridge
by Yunqi Z.
Fri, 02/15/2013 - 13:45 12
by Yunqi Z.
Mon, 02/18/2013 - 11:35
Normal topic How to get the L1, L2, and LLC miss rates from a Xeon 5140
by Guillermo Navarro
Thu, 05/31/2012 - 19:15 0
by Guillermo Navarro
Thu, 05/31/2012 - 19:15
Normal topic 32 byte store to load forwarding on Sandy Bridge
by Marcin K.
Wed, 03/05/2014 - 00:57 5
by iliyapolak
Tue, 03/11/2014 - 02:35
Closed topic Strange behaviour of Intel Xeon E3-1220v2
by Tommy F.
Tue, 05/14/2013 - 15:05 1
by Patrick Fay (Intel)
Tue, 05/14/2013 - 15:46
Normal topic Evaluating dfferent software prefetch schemes SandyBridge and later processors
by andy-nisbet
Wed, 07/25/2012 - 10:13 3
by McCalpin, John
Tue, 09/25/2012 - 15:53
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For more complete information about compiler optimizations, see our Optimization Notice.