Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
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Topic / Topic startersort descending Post date Replies Last Post
Hot topic DirectX11: big stalls in the driver of an Intel HD 3000
by DZ
Wed, 01/09/2013 - 03:33 26
by kecoro
Tue, 05/05/2015 - 01:17
Normal topic Disable C6/C7 C-state for core
by futureishere
Fri, 06/19/2015 - 05:45 5
by futureishere
Thu, 06/25/2015 - 01:06
Normal topic Disable onboard graphics to save power?
by Charlie H.
Mon, 04/03/2017 - 13:12 0
by Charlie H.
Mon, 04/03/2017 - 13:12
Normal topic Disable self-snoop on Intel CPUs
by le g.
Tue, 08/20/2013 - 23:17 0
by le g.
Tue, 08/20/2013 - 23:17
Normal topic DISABLE turbo boost
by Wei K.
Fri, 02/12/2016 - 06:44 1
by McCalpin, John
Fri, 02/12/2016 - 10:50
Normal topic Disabling cache coherancy
by balu.r.0212
Mon, 05/14/2012 - 04:00 2
by balu.r.0212
Wed, 05/16/2012 - 04:28
Normal topic Disabling Hardware Prefetch and Adjacent Cache Line Fetch in Sandy/Ivy Bridge without BIOS Support
by Adam J.
Wed, 07/31/2013 - 14:31 5
by iliyapolak
Tue, 08/06/2013 - 02:31
Normal topic disabling hardware prefetching on Xeon
by ramacn
Sun, 03/11/2012 - 12:49 3
by Patrick Fay (Intel)
Sun, 03/11/2012 - 18:12
Normal topic Disabling instruction cache
by Jog L.
Sat, 01/16/2016 - 03:19 3
by McCalpin, John
Tue, 01/19/2016 - 10:19
Normal topic Disabling Opportunistic Processor Performance for all Cores
by Samuel M.
Tue, 04/16/2013 - 10:16 9
by iliyapolak
Thu, 04/18/2013 - 10:32
Normal topic Disabling PMU counters NMI generation
by Patrick A.
Tue, 01/05/2016 - 00:26 5
by Patrick A.
Mon, 02/29/2016 - 01:04
Normal topic Disabling Prefetching on the i5
by chetreb
Mon, 11/26/2012 - 16:33 12
by Roman Dementiev...
Wed, 09/24/2014 - 23:40
Normal topic Disabling RAPL
by Mustafa K.
Thu, 02/25/2016 - 12:38 1
by McCalpin, John
Fri, 02/26/2016 - 09:10
Normal topic Disabling Turbo Boost
by Samuel M.
Mon, 05/20/2013 - 16:04 8
by Sergey Kostrov
Wed, 05/22/2013 - 17:04
Normal topic Disabling turbo boost for only some cores on a socket
by Travis D.
Tue, 01/31/2017 - 14:00 4
by Travis D.
Fri, 02/03/2017 - 12:17
Normal topic DMA scans with I/OAT have inconsistent results
by Timo D.
Tue, 12/05/2017 - 04:41 2
by Timo D.
Wed, 12/13/2017 - 01:01
Normal topic DMA synchronisation with incoming MWr-TLP
by Pay S.
Mon, 02/08/2016 - 06:55 0
by Pay S.
Mon, 02/08/2016 - 06:55
Normal topic Do intel cpus have options to speed up ipc ?
by Jog L.
Wed, 02/25/2015 - 08:05 2
by iliyapolak
Thu, 02/26/2015 - 22:37
Normal topic Do Older and Newer Intel Chipset Designed Motherboards Contain a Unique Serial Number
by victor6799
Tue, 09/20/2011 - 20:56 6
by Patrick Fay (Intel)
Thu, 09/22/2011 - 05:57
Normal topic Do PMUs occasionally lose their reliability?
by CciYu C.
Thu, 09/21/2017 - 20:24 1
by McCalpin, John
Fri, 09/22/2017 - 07:50
Normal topic Docs on Memory Controller PCI Configuration Space
by Wei W.
Mon, 10/07/2013 - 13:10 10
by iliyapolak
Thu, 10/10/2013 - 09:05
Normal topic Documentation on clock cycles for various Sandy Bridge instructions?
by christian.conve...
Wed, 01/18/2012 - 14:12 1
by Patrick Fay (Intel)
Wed, 01/18/2012 - 17:39
Normal topic Does any way to make the PMI to be a non-maskable ?
by Kelvin C.
Thu, 09/28/2017 - 04:42 2
by Kelvin C.
Thu, 09/28/2017 - 23:37
Normal topic Does disabling H/W prefetching affect prefetch/prefetchw instructions?
by Ming-Wei S.
Sun, 04/23/2017 - 15:19 2
by Tim P.
Wed, 04/26/2017 - 10:09
Normal topic Does EIST_TRANS work on Sandy Bridge?
by Alexander Alexeev
Mon, 08/19/2013 - 06:40 7
by Patrick Fay (Intel)
Sat, 08/24/2013 - 18:07
New posts
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Hot topic with new posts
Hot topic without new posts
Sticky topic
Locked topic
For more complete information about compiler optimizations, see our Optimization Notice.