Intel® Developer Zone:
Software Tuning, Performance Optimization & Platform Monitoring

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Discussion around topics such as monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, software characterization, software optimization techniques for performance and power/energy, monitoring CPU core and graphics processors and other system coprocessors as well asimmerging runtime usages for software metering and quality of service.
Intel monitors this forum Monday – Friday, 09:00 – 17:00 Pacific Time (GMT –7:00). Depending on the amount of research we need to do to track down the answer, it may take a day or two for us to respond.
Topic / Topic startersort descending Post date Replies Last Post
Hot topic Haswell L2 cache bandwidth to L1 (64 bytes/cycle)?
by Stephen
Fri, 10/03/2014 - 11:29 17
by John McCalpin
Thu, 08/06/2015 - 18:26
Normal topic Haswell loop alignment vs. unrolling
by Tim P.
Wed, 09/09/2015 - 05:49 2
by Tim P.
Wed, 09/16/2015 - 12:08
Normal topic Have a beeping problem with new ram memory.
by pinger d.
Sun, 03/30/2014 - 13:19 4
by iliyapolak
Mon, 03/31/2014 - 06:22
Normal topic help for tuning application's startup
by jinjunsheng
Tue, 10/18/2011 - 03:45 5
by iliyapolak
Thu, 02/14/2013 - 22:55
Normal topic Help me out..
by israfeal
Sat, 11/26/2011 - 09:17 5
by Patrick Fay (Intel)
Sat, 11/26/2011 - 09:17
Normal topic High number of retired instructions
by Tomer M.
Tue, 04/12/2016 - 06:45 2
by Tomer M.
Tue, 04/12/2016 - 07:09
Normal topic How 32 bytes alignment affect uop cache?
by Wei M.
Wed, 10/16/2013 - 15:35 6
by iliyapolak
Thu, 10/17/2013 - 10:50
Normal topic How branches in loop body affect the performance when unrolling?
by Peng Z.
Sun, 07/26/2015 - 23:36 3
by Tim P.
Tue, 07/28/2015 - 05:04
Normal topic How can i building Intel PCM without NMI watchdog check?
by Wenqin C.
Fri, 12/11/2015 - 01:43 3
by Wenqin C.
Sun, 12/13/2015 - 03:51
Hot topic How can I compile the MSR driver?
by Antonio v.
Thu, 02/21/2013 - 12:23 25
by iliyapolak
Sun, 03/23/2014 - 04:03
Normal topic How can i scale only one core's frequency in a multi-core processor?(Monitor through PMU)
by Songtao.H
Fri, 07/26/2013 - 04:58 9
by John McCalpin
Tue, 01/19/2016 - 09:43
Normal topic How can I understand the result of PMU
by Chenjie Y.
Sat, 08/24/2013 - 08:21 3
by Chenjie Y.
Sat, 08/24/2013 - 12:58
Normal topic How can we know two PMU events are contradicting with each other or not?
by Hao Shen
Sun, 07/07/2013 - 12:55 7
by Hao Shen
Tue, 07/09/2013 - 07:52
Normal topic How cycles are counted when instruction on core waits for data from memory?
by Alexander Alexeev
Tue, 07/30/2013 - 09:19 2
by iliyapolak
Thu, 08/01/2013 - 10:08
Normal topic how detect qpi and snoop traffic from system with 2way or more way westmere ex
by Black.S
Tue, 06/18/2013 - 08:32 10
by Black.S
Thu, 06/27/2013 - 09:59
Normal topic How does core get data from uncacheable memory?
by zhangyihere
Wed, 07/31/2013 - 08:15 3
by iliyapolak
Tue, 08/06/2013 - 02:46
Normal topic How does MacCPUID read Intel Turbo Boost Information?
by Samuel M.
Fri, 04/05/2013 - 10:49 3
by Patrick Fay (Intel)
Fri, 04/05/2013 - 16:10
Normal topic How does the shutdown on overheating work ?
by victor6799
Sat, 09/03/2011 - 22:11 8
by iliyapolak
Sun, 02/10/2013 - 21:51
Normal topic How Graphics Base Frequency Caluculate
by oniel-kumar (Intel)
Mon, 10/03/2011 - 09:47 1
by Hussam Mousa (Intel)
Mon, 10/03/2011 - 09:47
Normal topic How hardware prefetcher change load and store buffer behavior in processor pipeline
by Zhu G.
Mon, 06/29/2015 - 19:44 3
by John McCalpin
Wed, 07/01/2015 - 13:47
Normal topic How is the collection of MSR registers
by Black.S
Tue, 12/10/2013 - 09:30 12
by iliyapolak
Sat, 02/08/2014 - 07:14
Normal topic How is transmitted data assigned to a process by the ring bus system of Intel Sandy Bridge
by Steven P.
Mon, 10/12/2015 - 17:38 1
by John McCalpin
Tue, 10/13/2015 - 12:56
Normal topic How many pipeline stages detect branch mispredictions?
by T C
Tue, 07/07/2015 - 16:52 0
by T C
Tue, 07/07/2015 - 16:52
Normal topic How the LOCK CMPXCHG make sure the operation is atomic?
by Jacky Y.
Tue, 05/10/2016 - 08:38 0
by Jacky Y.
Tue, 05/10/2016 - 08:38
Normal topic How to alter the cache write policy while working with Intel X5675 series
by priyanka06
Thu, 06/28/2012 - 12:12 1
by Hussam Mousa (Intel)
Thu, 06/28/2012 - 16:27
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For more complete information about compiler optimizations, see our Optimization Notice.