Is there a way to disable cache coherency in intel sandybridge?
Hello balu,You can define a memory region as not cacheable. Then reads from and writes to that region of memory are not checked for coherency.Is this what you are looking for?Pat
I was thinking if there is a way to disable MESI protocol (but still take advantage of the cache beingavailable) that is typically used to address "false sharing". Assuming that i guarantee there will be no "false sharing", can i disable the protocol effects (overheads) induced by MESI.