Enabling and Disabling AVX in Visual Studio 2010 with Intel C++ Composer XE 2011

Enabling and Disabling AVX in Visual Studio 2010 with Intel C++ Composer XE 2011

Hai

Please help me in enbaling the SSE 3 and SSE 4.2 in visual studio 2010 ultimate. I am currently working on a sandy bridge processor based desktopplatform running on win 7 SP1. The AVX option is getting enabled through /arch:AVX command line option, but not SSE options. I just have options of enabling SSE and SSE2, not higher versions. I tried with/QxAVX, /QaxAVX,/arch:SSE, /arch:SSE2...when I tried to compile the code , it is ignoring these options. It is just accepting /arch:AVX. I want the SSE 3.0 and higheroptionsto be enabled in this tool.Do I need to write an intrinsic code for my application to enable these SSE3, SSE4.2instruction set support ?Please help.

Thanks
Rahul

6 posts / 0 new
Last post
For more complete information about compiler optimizations, see our Optimization Notice.

When you use /QxAVX or /QaxAVX, the compiler will try to generate the appropriate code if it think it proper.

It would be nice it you could provide a sample testcase.

Hi Rahul,

it would be also very helpful if you could provide the complete command line used for compiling the code. Note: Options /arch and /Qx are mutually exclusive.
How do you noticed that the compiler is ignoring the options?

Thanks,
Alex

Hi Rahul,

             So the issue here is that, You have not selected the Intel C++ compiler and you are using the Visual C++ compiler. Please select Intel C++ compiler and then goto Properties --> Code Generation [Intel C++] --> Intel Processor-Specific Optimization and then select the SIMD instruction set that you desire.

Regards,

Sukruth H V

Note: It looks like the 2nd thread with the same subject.

Rahul, Could you post your command line for review?

Also, here is a complete list of Intel C++ compiler options ( Version 12.1.7.371 Build 20120928 ) and you need to use SSE3 and SSE4.2 options I marked:

...
Code Generation

/Qx
generate specialized code to run exclusively on processors
indicated by as described below
SSE2 May generate Intel(R) SSE2 and SSE instructions for Intel
processors. Optimizes for the Intel NetBurst(R) microarchitecture.
SSE3 May generate Intel(R) SSE3, SSE2, and SSE instructions for
Intel processors. Optimizes for the enhanced Pentium(R) M
processor microarchitecture and Intel NetBurst(R) microarchitecture.
SSSE3 May generate Intel(R) SSSE3, SSE3, SSE2, and SSE
instructions for Intel processors. Optimizes for the
Intel(R) Core(TM) microarchitecture.
SSE4.1 May generate Intel(R) SSE4 Vectorizing Compiler and Media
Accelerator instructions for Intel processors. May
generate Intel(R) SSSE3, SSE3, SSE2, and SSE instructions
and it may optimize for Intel(R) 45nm Hi-k next generation
Intel Core(TM) microarchitecture.
SSE4.2 May generate Intel(R) SSE4 Efficient Accelerated String
and Text Processing instructions supported by Intel(R)
Core(TM) i7 processors. May generate Intel(R) SSE4
Vectorizing Compiler and Media Accelerator, Intel(R) SSSE3,
SSE3, SSE2, and SSE instructions and it may optimize for
the Intel(R) Core(TM) processor family.
AVX May generate Intel(R) Advanced Vector Extensions (Intel(R)
AVX), Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3,
SSE2, and SSE instructions for Intel(R) processors.
Optimizes for a future Intel processor.
CORE-AVX2
May generate Intel(R) Advanced Vector Extensions 2
(Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3,
SSE2, and SSE instructions for Intel(R) processors.
Optimizes for a future Intel processor.
CORE-AVX-I
May generate Intel(R) Advanced Vector Extensions (Intel(R)
AVX), including instructions in Intel(R) Core 2(TM)
processors in process technology smaller than 32nm,
Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE
instructions for Intel(R) processors. Optimizes for a future Intel processor.
SSSE3_ATOM
May generate MOVBE instructions for Intel processors,
depending on the setting of option /Qinstruction.
May also generate Intel(R) SSSE3, SSE3, SSE2, and SSE
instructions for Intel processors. Optimizes for the
Intel(R) Atom(TM) processor and Intel(R) Centrino(R)
Atom(TM) Processor Technology.

/QxHost generate instructions for the highest instruction set and processor available on the compilation host machine

/Qax[,,...]
generate code specialized for processors specified by
while also generating generic IA-32 instructions.
includes one or more of the following:
SSE2 May generate Intel(R) SSE2 and SSE instructions for Intel processors.
SSE3 May generate Intel(R) SSE3, SSE2, and SSE instructions for Intel processors.
SSSE3 May generate Intel(R) SSSE3, SSE3, SSE2, and SSE
instructions for Intel processors.
SSE4.1 May generate Intel(R) SSE4.1, SSSE3, SSE3, SSE2, and SSE
instructions for Intel processors.
SSE4.2 May generate Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2,
and SSE instructions for Intel processors.
AVX May generate Intel(R) Advanced Vector Extensions (Intel(R)
AVX), Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3,
SSE2, and SSE instructions for Intel(R) processors.
CORE-AVX2
May generate Intel(R) Advanced Vector Extensions 2
(Intel(R) AVX2), Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3,
SSE2, and SSE instructions for Intel(R) processors.
CORE-AVX-I
May generate Intel(R) Advanced Vector Extensions (Intel(R)
AVX), including instructions in Intel(R) Core 2(TM)
processors in process technology smaller than 32nm,
Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel(R) processors.
/arch:
generate specialized code to optimize for processors indicated by
as described below
SSE2 May generate Intel(R) SSE2 and SSE instructions
SSE3 May generate Intel(R) SSE3, SSE2 and SSE instructions
SSSE3 May generate Intel(R) SSSE3, SSE3, SSE2 and SSE instructions
SSE4.1 May generate Intel(R) SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions
SSE4.2 May generate Intel(R) SSE4.2, SSE4.1, SSSE3, SSE3, SSE2 and SSE instructions
AVX May generate Intel(R) AVX, SSE4.2, SSE4.1, SSSE3, SSE3,
SSE2 and SSE instructions
IA32 generate x86/x87 generic code that is compatible with IA-32
architecture. Disables any default extended instruction
settings and any previously set extended instruction settings.
SSE same as /arch:IA32
/Qinstruction:
Refine instruction set output for the selected target processor
[no]movbe - Do/do not generate MOVBE instructions with SSSE3_ATOM
(requires /QxSSSE3_ATOM)
...

I don't read the original post entirely the same as Sergey did.

In order to support SSE3 and SSE4.2 intrinsics, it's sufficient to set /arch:SSE4.2 option (after switching the project to Intel C++)

I see no point in a multi-architecture target, as the SSE4 intrinsics have to be rejected when building for SSE3 target.

Those quotations which Sergey posted seem to drive home the lack of documentation upkeep with each supported architecture described in pre-release terminology which has become misleading.

I'm not sure that OP understands that the Intel compilers all along have supported auto-vectorization according to  /arch: or earlier equivalents, while Visual Studio compiler itself didn't auto-vectorize at all until VS2012, and for that purpose supports only /arch:SSE2 and AVX (as there no longer is so much benefit to adding intermediate ones to the mix).

It seems rather late in the game to learn intrinsics programming at SSE3 and SSE4 level and fail to take the hint from Microsoft.

Leave a Comment

Please sign in to add a comment. Not a member? Join today