MSI: Message Address Register: Redirection Hint

MSI: Message Address Register: Redirection Hint

Section 10.2 of Vol. 3 (Edition -31), Message Signalled Interrupts, is not particularly clear on the purpose of the Redirection Hint bit in the Message Address Register. The text makes clear that if RH is 1, the destination mode (DM) bit determines whether physical or logical addressing shall be used, and that the broadcast address shall not be used.

However, if RH is 0, it says "then the DM bit is ignored and the message is sent ahead independent of whether the physical or logical destination mode is used." (end of 10.12.1) What is that supposed to mean?

The text also does not indicate the proper value of the most significant 32 bits of the Message Address Register (the Message Upper Address Register)---probably all zeros.

Finally, 10.12.2 says that reserved fields must be preserved on writes. This must be wrong, the fields should be MUST-BE-ZERO. Which agent in the system will have initialized them to a non-default value? The PCI device can't have, since the contents of the Mesage Address and Data Registers are processor-specific. If the BIOS were to initialize these fields, it would enable functionality that the operating system is unaware of. New features are normally enabled by setting some enablement bit, making MUST-BE-ZERO the right choice.

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David Ott

Here is the comment I received:

"The Message Address register for MSI and MSI-X are written by the OS in cooperation with the device driver for the device. Sometimes the device driver is not even involved. In Windows WDM for example, the PCI bus driver would take care of this.

Section 10.11.1 of the vol 3a APIC section states that if RH is 0, the interrupt is delivered to the processor whose ApICID matches the value in the Destination ID Field.

What version of the IA32 SDM are you referring to?. The March 2010 version vol 3a has 10.12.2 mapping to x2apic."

David Ott

Hi David,

thanks for your efforts.

As stated in my original comment, I referred to Edition 31.
Edition 34, released March 2010, is identical to Edition 31
concerning message signaled interrupts.

With all due respect, the comment doesn't address my question.
I understand the role the message address register plays in
MSI and am not interested in how the Windows WDM deals
with it.

N.B. 10.11.1 says "The format of the Message Address Register
(lower 32-bits) is shown [below]". Neither MSI nor MSI-X define
a 64-bit message address register, it is always 32-bits wide,
both in PCI and PCI Express. The message address register
can optionally be 64-bits wide.

The exact quote from 10.11.1 is "When RH is 0, the interrupt is
directed to the processor listed in the Destination ID field."
This does not specify if physical or logical addressing mode is used.

Experimentation shows that physical addressing mode is used
with RH equal to zero.

10.11.1 goes on to say that "When RH is 1 and the physical destination
mode is used [i.e., DM = 0], the Destination ID field must not be set to 0xFF; it must
point to a processor that is present and enabled to receive the interrupt."

This would seem to be the exact same case as RH equal to zero;
there, DM is ignored: "If RH is 0, then the DM bit is
ignored and the message is sent ahead independent of whether
the physical or logical destination mode is used."

However, changing RH to 1 and DM to zero fails to send the message
to the physical processor.

Perhaps you could prod your contact into shedding some more
light on this subject---readers of the SDM would benefit.

Konrad Schwarz

Another comment I received:

"The problem is that the same devices have to work with Itanium and x86. Itanium does not support logical mode but does support redirection of physical mode interrupts instead. X86 supports logical mode but does not support redirection of physical mode interrupts. I think they should have just said RH=1 is not defined in physical mode, but instead they are trying to tell you what the restrictions are if you set it on. Since people may want to build interconnects that support both sets of processors they probably did not want to say anything that might cause people to build devices that would not work on Itanium. For X86 physical mode interrupts the same thing is going to happen if the bit is set or not set. The reference to the APIC ID being 0xff is because 0xff is broadcast and lowest priority (what the RH bit really is for X86) is illegal with broadcast."

David Ott

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