cache size?

cache size?

softarts's picture

to avoid false-sharing,need to add some 'pad' data between / before / after theshare variable,

I have checked the TBB code, it define ALIGNED_SIZE 64 (64 is common size of cache line),

will the cache linesize vary with different CPU platform? i.e. Core2 ,XEON,and XEON 5500?

ps:Core2 has 64Kcache while XEON has 2M,right?

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Thomas Willhalm (Intel)'s picture

Quoting - softarts
to avoid false-sharing,need to add some 'pad' data between / before / after theshare variable,

I have checked the TBB code, it define ALIGNED_SIZE 64 (64 is common size of cache line),

will the cache linesize vary with different CPU platform? i.e. Core2 ,XEON,and XEON 5500?

ps:Core2 has 64Kcache while XEON has 2M,right?

The cache line size is the same inall threecases: 64 Bytes. This is what counts for false sharing.

The size of the last-level cache varies a lot: 4MB per 2 Cores for Intel Core2 processor QX6850 and Intel Xeon processor 5300 series, 6MB per 2 Cores for Intel Core2 processor QX9770 and Intel Xeon processor 5400 series, 8MB per 4 cores for Intel Core i7-965 and Intel Xeon processor 5500 series. A complete list can be found at http://processorfinder.intel.com/.

Kind regards
Thomas

softarts's picture

Quoting - Thomas Willhalm (Intel)

The cache line size is the same inall threecases: 64 Bytes. This is what counts for false sharing.

The size of the last-level cache varies a lot: 4MB per 2 Cores for Intel Core2 processor QX6850 and Intel Xeon processor 5300 series, 6MB per 2 Cores for Intel Core2 processor QX9770 and Intel Xeon processor 5400 series, 8MB per 4 cores for Intel Core i7-965 and Intel Xeon processor 5500 series. A complete list can be found at processorfinder.intel.com.

Kind regards
Thomas

why can not find L1 cache information on the URL?
the L1 cache (I&D) are always 32+32 KB?
thanks!

Thomas Willhalm (Intel)'s picture

Quoting - softarts
why can not find L1 cache information on the URL?
the L1 cache (I&D) are always 32+32 KB?
thanks!

Yes, L1 cache(I&D) are always 32+32 KB on current Xeon and Core architecture. (Itanium and the old P4 architecture are different.)

Kind regards
Thomas

softarts's picture

just check the lastest TBB code(20091101)

the #define ALIGNED_SIZE 64 disappeared (tbbmalloc)

and it deinf NFS_LINESIZE 128 (cache_aligned_allocator.cpp)

why does it happen?

Raf Schietekat's picture

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