For the Intel Xeon Quad-Core Processor X5482 (12M Cache, 3.20 GHz, 1600 MHz FSB) there are two steppings concurrently available. Which is really the best purchase $2800 a pair? I'm building a workstation to be used R&D, Hardware and Software ptototyping. Also to used as test bed for portotypes.
I've spent a couple months (like 3 or 4), over the Intel website, email tech support, chat tech support, all of the comparision tools, read through the the technical documents (data sheets, specifications, specification updates, errata, design guides, Thermsl-Mechanical design guides, Platform technologies, information summaries,Intel New Technologies, Integration overviews and recommendations,some of the immediatly relevent programming guides, X5400 assoiciated Intel technologiessuch as RAID, Matrix Storage, Intel platform memory, dual processing, multiprocessing, parallal programming, performance briefs, white papers,technical advisories, the shocking horrors of legacy lagacy (programmed IO aaah!!!), trouble shooting, debugging, everything I could could find at Intel.com, plus outside references Like intel technical books, Microsoft, Supermicro, many venders, and googled the planet
for the: X5482 CPU, 5400 MCH, 631ESB/632ESB IO controller Hub, 6700PXH 64-bit PCI Hub, 6402/6404 AMB, the 800MHz FB DDR2 SDRAM DIMMs, and the Supermicro X7DWA-N motherboard.
(Note: SLANZ = C0 stepping, SLBBG = E0 stepping)
But the the only Differences I can determine bewteen the SLANZ and the SLBBG are as follows:the The older steping ( by two cores) SLANZ has Intel I/OAT, Enhanced Halt state C1E, Intel Thermal Monitor 2, and a higher VCC @ 150watts (the SLBBG is 130 watts with alower VCC). We can cross out Matrix storage technology since the 6311/6321ESB do not support. Also if you have the6311 ESB you loose Intel
I/OAT since it does not support that.
There is this to consider: according to the summary table of changes errata tableXEON 5400 series, in the XEON 5400 series specfication update , the E0 stepping had some fatal problems ( AX45, AX47 hang the CPU, AX48 puts CPU in unknown state) that the C0 does not have.
The C0 steping has 5 problems the E0 stepping doesnot.
And the E stepping has 8 errors the C0 stepping does not.
One error in the EO stepping I think may make Digital Thermal sensor not readable because of a problem reading it via PECI. Ifthat's true, it may imply that PWM fan controlalgorythems are applicabil.
However, I thought, there was a footnote or comment somewhere the errata that says theerratam occureunder test vectors conditionsthat werenot likely to occurewhen executing native software.
My question is this: what are the intentional functional changesin the E0 from the C0??
Is the E0 on the verge of some releasing some Intel new techknlogies?
Like,some Intel new techknlogies might me fully implimented with a future update downdload of microcode firmware to the E0 core??
How real are the erratium?
Do the functioning features of the C0 stepping outway the newer cores of the E0 stepping.
I was hoping that X5482 design engineer might know of the top of his head.
I'm spending about $15,000 onthis developmentstation in hardware and software parts. I want to push the most performance that is possible out of the delevelopmentstation beacuse nobody wants you to design last months anything.
I'm an hardware software design engineering contractor and I've been designing hardware and software since the (don't laugh) Intel 8080.
Thank you for your time, Michael vallino firstname.lastname@example.org
PS I was direccted to this software forms webpage by tech support on serveral occasions. If this an inappropriate form, please excuse me. And could you direct me to the correct form webpage.