Beta Course Design Document: Examples of Concurrent Solution Design

Beta Course Design Document: Examples of Concurrent Solution Design

Selwyn You (Intel)'s picture

To All -
Please find a beta version of the Course Design Document for a short module that illustrates concurrent solution design patterns and methods by algorithm examples. Please read and comment freely.



1. Module Name: Examples of Concurrent Solution Design


2. Writers: [Intel Confidential List]


3. Targeted availability: Sep.30th 2008


4. Brief Module Description


Proposed duration: 1.5 hours.


Given that multi-core platforms have become mainstream, teaching software developers to make this adjustment emerges as a well-recognized challenge. One reasonable solution to this challenge is to illustrate the essential techniques using examples of well known applications or algorithms.


This lecture-only module illustrates the parallel solutions by means of discussion and instructor demonstration.. The lectures cover the work load partitioning methods for the typical program constructs of iteration, recursion, and function (call). The examples used for case study are known numeric algorithm of Least Square Estimation, encryption algorithm Huffman Coding and implementation of a Spell Checker.


The examples in this module will enrich the case study base that arecurrently in use for standard concurrent/parallel programming curricula.


5. Needs Analysis


Though parallel programming practices have existed for decades, they are not familiar to software developers out of the High Performance Computing (HPC) world. It is a challenge to bring those practices to the mastery of main stream developers.


On the other hand, examples or case studies are an excellent, proven means of providing relevant illustrations for learners. This module presents the concurrent solution design methodsregarding common design constructs using examples of popular applications and known algorithms.


With this approach, the audience scope is enlarged to any programmer who has acquired basic knowledge of programming language and algorithms, and who would like to gain performance advantages through parallelization.


6. Subject Matter Experts (SMEs)


[Intel Confidential List]


7. Learner Analysis


The ideal student for this module is an adult learner at a university, who in addition to exhibiting the learning characteristics of adult learners, has also the following traits:


Has been a programmer in the C/C++ and/or other programming languages (Java), who has at least 1 year programming experience (or the equivalent)



oCould be a freshman, or sophomore or junior level programmer (1st, 2nd or 3rd year college student), or an advanced younger student
oIs able to routinely write simple sorting or computation programs (between 10 and 100 lines) from scratch in a day or less, with no difficulty whatsoever
oIs able to compile and run the developed program with corresponding software tools (like editor, and compiler etc) on any operating system environment


Has the ability to describe at least a high-level algorithmic solution to a given computational problem.



oIs currently or will soon be an application developer.


Has the abilit
y to learn from lecture/discussion environment only.


Has an ability to generalize from examples.


Demonstrates a willingness to tackle a difficult concept and deal with complexity.


a. Special notes for Faculty Training learners/attendees

Faculty Training (FT) attendees are special cases wherein they likely have more experience than the usual target audience for this class, and, they have the immediate goal of teaching this class in a live classroom environment with targeted students.

Ideal FT candidates for this material have the following traits:



Have an understanding of the issues of parallel programming and are at least familiar with one concurrent programming method
Currently instruct or plan to instruct adult students who fit in the learner description earlier in this section
Currently using a successful programming curriculum, or intend to soon create or teach one


8. Context Analysis


The purpose of a Context Analysis is to identify and describe the environmental factors that inform the design of this module. Environmental factors include:



1.Media Selection: lecture presentation will be in Microsoft* Power Point* format including speaker notes. Lab source and the corresponding guide or document for demo purpose will be provided.
2.Learning Activities: Lecture presentation plus instructor demonstration; discussion of similarities and differences between models presented is encouraged between students and between students and instructor.
3.Participant Materials and Instructor/Leader Guides: Minimal instructor notes are included in Power Point Notes sections. Recorded presentation and lecture notes for the slides, narrated by course author, will be made available if they are requested.
4.Packaging and production of training materials: Materials are posted to Intel Academic Community website, for worldwide use and alteration
5.Training Schedule: The module is 1.5 hours.


9. Task Analysis


The relevant Job/Task Analysis for this material is defined by the Software Engineering Body of Knowledge (SWEBOK) and can be viewed in detail here: http://www.swebok.org


The primary Bodies of Knowledge (BKs) used include, but are not limited to:


Software Requirements BK


Software Design BK



oKey issues in Software Design (Concurrency)


oData persistence, etc.


Software Construction BK



oSoftware Construction Fundamentals


oManaging Construction


oPractical Considerations (Coding, Construction Testing, etc.)


Relevant IEEE standards for relevant job activities include but are not limited to:


Standards in Construction, Coding, Construction Quality IEEE12207-95
(IEEE829-98) IEEE Std 829-1998, IEEE Standard for Software Test Documentation, IEEE, 1998.
(IEEE1008-87) IEEE Std 1008-1987 (R2003), IEEE Standard for Software Unit Testing, IEEE, 1987.
(IEEE1028-97) IEEE Std 1028-1997 (R2002), IEEE Standard for Software Reviews, IEEE, 1997.
(IEE
E1517-99) IEEE Std 1517-1999, IEEE Standard for Information Technology-Software Life Cycle Processes- Reuse Processes, IEEE, 1999.
(IEEE12207.0-96) IEEE/EIA 12207.0-1996//ISO/IEC12207:1995, Industry Implementation of Int. Std. ISO/IEC 12207:95, Standard for Information Technology-Software Life Cycle Processes, IEEE, 1996.


10. Concept Analysis


Work partitioning strategies



oData decomposition
?Iterative scenario
?Recursive scenario
?Functional scenario (thread safe library design)


oSub-tasking decomposition


Dependency, and Communication/Synchronization analysis


11. Learning Objectives


Given an algorithm to a known problem, identify the appropriate concurrent/parallel solutions for recognized constructs as discussed during class. Further, students will be able to defend their choices using the vocabulary established during class. The constructs the students will be able to identify include Iteration, Recursion, and Function (call).


Given a series of partitioned modules, identify the dependencies, communications, and synchronization events between them, as defined in the course materials. Further, students will be able to defend their choices using the vocabulary established during class.


12. Criterion Items


Q: What is a proper parallel solution for iterative type of application?
A: Data decomposition.


Q: What is a possible parallel solution for recursive type of application?
A: Data decomposition.


Q: What is a possible parallel solution for applications involving function invocation?
A: Data decomposition.


Q: What should be avoided in design of a thread safe library?
A: [there could be other precautions but this is the least to be mentioned] Shared variables for routine states should be avoided.


13. Expert Appraisal


This Content Design Document will be posted to the Intel Academic Community forum with an invitation to solicit comments from readers of the forum. Additionally, new focused SME review from outside the company will be solicited and used.


14. Developmental Testing


Planned alpha and beta material will be posted to the ISC website will be Sep.17th, 08.


15. Production


Upon completion and successful passing of the Product Readiness Approval in the PDT, the materials produced for this module will be posted to the Intel Academic Community (IAC) website. There they will be available for download by IAC registered participants.

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