Bit Field Alignment

Bit Field Alignment

Ihave a structure containing bit fields

struct x{ // 12 bytes
unsigned int a[2];
U8 b;
unsigned int c:12, d:12;
};

When compiled with Intel compiler 9.1 it uses more memory than MinGW g++ 3.4.5. I suspect this is due to bit field tail padding. Is there any way the Intel compiled structure size to be exactly 12 bytes?

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I guess you are using ICL for Windows, so you will not have the same pack/alignment options as g++. Did you try /Zp4?

I am surprised that MinGW would still not have default alignments set to support parallel SSE.

Yes, i am using ICL for Windows. I have already tried /Zp4 and memory allocation is exactly the same as with the default alignment option. /Zp2 and /Zp1 result in less memory allocated, but still not the optimum 12 bytes.

The real question is not why MinGW has not default alignments set to support parallel SSE, but why ICL does not have an option to support bit packed alignment. When memory usage is paramount such an option would be very useful.

Unless there is an other way, i will have to resort to MinGW despite the fact it produces slower code.

try using something like

#pragma pack(1)

struct x{ // 12 bytes
unsigned int a[2];
unsigned int wasU8 : 8;
unsigned int c:12, d:12;
};


Jim Dempsey

www.quickthreadprogramming.com

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