Trace cache and self-modifying code

Trace cache and self-modifying code

IA-32 Software Developer's Manual says:

For the Pentium 4 and Intel Xeon processors, a write or a snoop of an instruction in a code segment, where the target instruction is already decoded and resident in the trace cache, invalidates the entire trace cache.

Does every executed instruction get into the trace cache? If an instruction, which was executed only once but very recently, is modified, will that invalidate the trace cache?

Does this also mean that if code is read as data, the trace cache can be invalidated?

Are algorithms used by trace cache in Intel's processors described anywhere?

Thanks

3 posts / 0 new
Last post
For more complete information about compiler optimizations, see our Optimization Notice.

Greetings from Intel Software Network Support. We are forwarding your question to our engineering contacts, and will let you know how they respond.

Regards,

Lexi S.
Intel Software Network Support
http://www.intel.com/software/
email: ISN.support@intel.com
*Other names and brands may be claimed as the property of others.

Greetings from Intel Software Network Support. You are asking for details that may be covered under NDA. Feel free to send yourquestion directly to Intel Software NetworkSupportthrough the support linklisted below, and we will be sure to get you a timely answer to your questions.

If your company wishes toenroll for membership in the Intel Software Network'sEarly Access Program, you may go to the Early Access Program page at http://intel.com/cd/ids/developer/asmo-na/eng/eap/19383.htmand apply on-line.

I hope thiswill giveyou the information that you seek.

Best regards,

Jim A.
Intel Software Network Support
http://www.intel.com/software/
Contact us
*Other names and brands may be claimed as the property of others.

Message Edited by intel.software.network.support on 11-15-2005 11:09 PM

Leave a Comment

Please sign in to add a comment. Not a member? Join today