Prescott 0xF41+ and TSC speed

Prescott 0xF41+ and TSC speed

I have a question that nobody can answer at this time and I would love to know more about this.

It seems that, whatever the multiplier is, the internal clock speed reported by TSC is always reported at its maximum. (I.E. for a 3.8 GHz Prescott F41 running at 14*200, the TSC still works at 3.8 GHz while the CPU is
working at 2.8 GHz)

As we use TSC to compute internal clock speed, the reported frequency
is always reported at its maximum value, independently of the current multiplier, that causes the fsb to be wrong, of course, when you tryed to compute FSB by : (Freq by TSC)/ Multiplier.

Have you got some more informations about change done on the TSC in this new Prescott Core ? This "issue" does NOT occur with the old Northwood core (We tryed with a Mobile Northwood that allow multiplier change by EIST) but still occur in Prescott F43 (6xx Serie) and on Smithfield CPU...

Thank you,
____________________________________
Samuel DEMEULEMEESTER - UIN : 210384
Chief Editor : http://www.x86-secret.com
Developer : http://www.memtest.org

Message Edited by S_DEMEULEMEESTER on 02-14-2005 11:21 AM

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Last post
For more complete information about compiler optimizations, see our Optimization Notice.

We are forwarding your question to our engineering contacts and will let you know how they respond.

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

Message Edited by intel.software.network.support on 12-01-2005 10:32 AM

Samuel,

The answer to this includes Intel confidential information,so we are unable topost the resolution to this board.

Generally speaking, requests forIntel confidential documentation can be submitted through one's Intel representative, who can ensure that the required non-disclosure agreements are in place.

We will contact you directly by email to help set this up.

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

Message Edited by intel.software.network.support on 12-01-2005 10:32 AM

Hello,

Thank you for your email and quick answer.

I understand that 6xx and smithfield are not yet released and you can't comment on them. I should not have written about them.

By the way, the Pentium 4 'J' serie, based on the Prescott F41 core, is an offical, announced Intel product and I noticed that the specifications for TSC does NOT seems to follow the Intel guideline for TSC as described in "IA-32 Intel Architecture Software Developers Manual - Volume 2B" for RDTSC (Page 162) and, especially in "IA-32 Intel Architecture Software Developers Manual - Volume 3", section 15.8 "TIME-STAMP COUNTER".

In order to help the online Intel developer's community who can face this question, I just wondered why. So, I hope there is no confidentials informations about this basic, documented feature, present on all current Intel CPUs and used in many software.

This important change in a widely used fonctionality is not yet documented by Intel and can cause stranges behaviors. That's why I think developers must be aware of possible, unexpected results while using TSC on newer Pentium 4.

In any case, thank you for your valuables informations.
____________________________________
Samuel DEMEULEMEESTER - UIN : 210384
Developer : http://www.memtest.org

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