Does delivery mode 101 (INIT) work for the Performance Management Interrupt in the local APIC of a Pentium 4? (using the LVT entry at address FEE00340h).
Deliver modes 000 (Fixed) and 100 (NMI) work with my logic, but if I change the deliver mode to 101 and set the vector field to 0, the counter runs and overflows at the expected time but *no* INIT request is generated by the APIC. Furthermore, bit 16 of the LVT entry for the PMI does *not* transit from 0 to 1 at counter overflow time (contrary to the documentation), but bit 31 (OVF) in the CCCR for the counter does transit from 0 to 1 at this same time (in agreement with the documentation.) I am using the MSR_BPU_COUNTER0 counter with the global_power_events event to count clockticks when the processor is active.
I am developing my code using document 253668, "IA-32 Intel Architecture Software Developer's Manual, Volume 3, System Programming Guide", dated 2004, as the definitive reference for the APIC and the Performance Management counters, etc. Chapter 8 seems to indicate that the INIT delivery mode is available for the PMI. I cannot find any contraindications to using the INIT mode, either in this manual nor in the other manuals of the same series, nor in any specification updates or errata.
I have been developing and testing my logic on a Family F, Model 2, Stepping 7 processor, in real mode. My application requires the INIT delivery mode for a PMI, the other modes or interrupts will not provide the true watchdog timer I am trying to implement for my embedded code.