DESCRIPTION: ICACHE.MISSES is an event that counts the number of times there is a miss in the instruction cache.
RELEVANCE: Instruction cache misses cause a significant number of stall cycles when the instruction data is not in the desired cache and retrieval requires access from main memory. Instruction cache misses generally cause the most delay (over data cache misses) because the processor has to wait until the instruction is fetched from main memory. Instruction cache misses can happen often with self-modifying code.
SOLUTION: In order to prefetch the data in advance to ensure availability in the instruction cache when desired, the following can be done to reduce the number of instruction cache misses:
- Raising the optimization level passed to the compiler. Profile guided optimizations are particularly beneficial as it enhances the optimization decisions the compiler makes regarding instruction cache utilization and memory paging.
- Inserting prefetch intrinsics into the source appropriately
- Repositioning function calls in source code to group calls that call each other together and increase the likelihood of instruction cache hits
- Avoid unrolling loops excessively