Back End Memory Bound

Back End Memory Bound

TITLE: Back End Memory Bound

ISSUE_NAME: Backend^MemBound

DESCRIPTION:

Cycles the back end was bound in the memory hierarchy

RELEVANCE:

This metric represents how often the pipeline was back end bound somewhere in the memory hierarchy.  Memory Bound describes cycles when there is a non-completed in-flight memory demand load which coincides with execution starvation (nothing is executing). Note that we account only for demand load operations as uops typically do not wait for (direct) completion of stores or hardware prefetches. To calculate this, we use a new counter available in the Intel processor codename Ivy Bridge:

Memory Bound: CYCLE_ACTIVITY.STALLS_LDM_PENDING / CPU_CLK_UNHALTED.THREAD

CYCLE_ACTIVITY.STALLS_LDM_PENDING counts whenever there is an execution stall and the Load Matrix (LDM) was not empty, thus it is a subset of CYCLE_ACTIVITY.CYCLES_NO_EXECUTE.  The load matrix has an entry for every non-completed load.

EXAMPLE:

For instance, if you had LLC misses, you would see a high back end memory bound percentage

SOLUTION:

RELATED_SOURCES:

NOTES:

EQUATION:  CYCLE_ACTIVITY.STALLS_LDM_PENDING / CPU_CLK_UNHALTED.THREAD

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For more complete information about compiler optimizations, see our Optimization Notice.

Is CYCLE_ACTIVITY.STALLS_LDM_PENDING increased in TSC? Would it be influenced by frequencies?

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