Back End Bound Due To Latency Caused By L2 Cache

Back End Bound Due To Latency Caused By L2 Cache

Charlie Hewett (Intel)'s picture

TITLE: Back End Bound Due To Latency Caused By L2 Cache

ISSUE_NAME: Backend^MemBound^L2Bound

DESCRIPTION:

Cycles the back end was bound on the L2 cache

RELEVANCE:

This metric represents how often the pipeline was back end bound on the L2 cache.  Avoiding cache misses (i.e. L1 misses/L2 hits) will improve the latency and increase performance.

EXAMPLE:

For instance, if you have many L1 misses and hit in the L2 cache, you would see a high percentage of back end memory bound percentage in L2.

SOLUTION:

RELATED_SOURCES:

NOTES:

EQUATION:  (CYCLE_ACTIVITY.STALLS_L1D_PENDING-CYCLE_ACTIVITY.STALLS_L2_PENDING) / CPU_CLK_UNHALTED.THREAD

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