Where to read about DMA Protected Range (DPR)?

Where to read about DMA Protected Range (DPR)?

In this doc:

http://www.intel.com/content/dam/www/public/us/en/documents/guides/intel...

It says:

"The DMA Protected Range (DPR) is a region of contiguous physical memory whose last byte is the byte before the start of TXT segment (TSEG), and which is protected from all DMA access. The DPR size is set and locked by BIOS. "

Where can I find information about DPR? Because it also says:

"The MLE itself may reside in the DPR as long as it does not conflict with either the SINIT or heap areas. If it does reside in the DPR then it need not be covered by the Intel VT-d Protected Memory Regions."

So naturally to make things simple on myself, I would like to not have to deal with VT-d, by just placing my MLE in the DPR. But that implies I know how to look up the range of DPR, and I have not been able to come up with anything based on googling. (Unless DPR is actually this "DMAR" I've seen other references to?)

Thanks

JB

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Oh and one more question is, does TSEG really stand for "TXT Segment"?! Because I was wunder the impression TSEG was only used for SMM.

JB

OK, never mind. I found the DPR in the CPU manuals (duh. I was looking at the PCH manual first, which doesn't make any sense.) FWIW though in the 3rd gen core manuals at least "DPR" = "DRAM Protected Range" != "DMA Protected Range", which is probably why googling wasn't working. Should get the TXT document references above to fix the acronym.

Thanks

JB

Nice. And then at the end of the manual it goes back to being "DPR - DMA Protected Range Register"

JB

OK, I read the manual forward and back, but the question still isn't answered. If we look at something like this:

https://www-ssl.intel.com/content/dam/www/public/us/en/documents/datashe...

It says things like:

"

The DPR range works independent of any other range, including the PMRC checks in
VTd. It occurs post any VTd translation. Therefore, incoming cycles are checked against
this range after the VTd translation and faulted if they hit this protected range, even if
they passed the VTd translation.
The system will set up:
• 0 to (TSEG_BASE – DPR size – 1) for DMA traffic
• TSEG_BASE to (TSEG_BASE – DPR size) as no DMA."

A reference to needing to set a DPR size.

and then "TSEG_BASE

The “TSEG_BASE” register reflects the total amount of low addressable DRAM, below
TOLUD. BIOS will calculate and program this register; so, the system agent has
knowledge of where (TOLUD) – (GFX stolen) – (GFX GTT stolen) – (TSEG) is located.
I/O blocks use this minus DPR for upstream DRAM decode."

Again a reference to the size.

But when we get down to the next DPR reference of significance, in "2.5.16 DPR—DMA Protected Range Register", the only options are "Enable Protected Memory (EPM)" and "Protected Region Status (PRS)".

There is no mention of size. And no more mentions of DPR.

So the original question stands. How can I look up what the current DPR size is?

Thanks

JB

...Test to see if it was the URL or the multiple posts which got my other msg queued... ;)

JB

And then I figured I should check how xen or tboot does it. Which lead me to "TXTCR_DPR" which lead me to http://software.intel.com/en-us/forums/topic/290536 which lead me to finding out that the DPR range is actually defined later on in the MLE dev guide itself!

SO! I think this runaround could have been avoided with a forward link to later in the document when the DPA range is first mentioned in the overview ;)

JB

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