How to load 16 copies of an integer variable into a Xeon Phi vector register

How to load 16 copies of an integer variable into a Xeon Phi vector register

 

There is a broadcast instruction for float 32 values but does not seem to be one listed for int32 values

 

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I believe VMOVDQA32 does.

Corresponding intrinsic _mm512_extload_epi32/ _mm512_mask_extload_epi32 (http://software.intel.com/en-us/node/461066) discusses more.

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