I haven't had time to experiment yet, but the various documents seem to indicate conflicting information about X87 (scalar "old" FPU) instructions supported on Xeon Phi.
Here is the jist of my question: Some of the documents list the X87 as being run independent of the vector floating point. By this I mean not using any of the resources of the vector floating point system. IOW it appears that a core could conceivably have concurrent AVX512 and X87 instructions executing. This is unlike what it is on the IA32 and Intel64 platforms.
Is the above true?