I'm considering using memory type aliasing (with PAT) in order to map same IO memory region both as UC and WC (with different virtual/linear address). I'd like to do it because in some cases it's better to have strong ordering for it, and weak ordering in others.
Intel SDM it says that "... it is possible to have a single physical page mapped to two or more different linear addresses, each with different memory types. Intel does not support this practice because it may lead to undefined operations ...". Is it discouraged because the processor can have undefined behavior in this case, or because i can have memory consistency issues if i don't take care of ordering/consistency myself?