Xeon Phi Register Manual

Xeon Phi Register Manual

Hi,

We are planning to get the Xeon Phi working in our research environment which is a non-linux / non-windows operating system. Therefore we need to write our own drivers and our driver model is quite different to the one used in Linux / Windows. We have looked at the available documents for the Xeon Phi, however from a systems point of view they are pretty disappointing. 

Is there something like a technical reference manual / register reference of the Xeon Phi containing all the available registers on host side / coprocessor side ?

Thanks.

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Have you taken a look at the Instruction Set Architecture for the coprocessor?

Quote:

Sumedh Naik (Intel) wrote:

Have you taken a look at the Instruction Set Architecture for the coprocessor?

I've encountered this document, but this is not what we we are looking for. For now, we are not interested in the floating point unit and vector instructions.

The information we're looking for contains the register specification for the GBOX, SBOX, host side configuration registers and so on. Something like Appendix: SBOX Control Register List of the System Software Developers Guide but with much more detail.

Got it. Let me look around and get back to you with what I find? 

Quote:

Sumedh Naik (Intel) wrote:

Got it. Let me look around and get back to you with what I find? 

I appreciate your help. Let me know when you've found something.

Something like the 82599-10-gbe-controller-datasheet [1] chapters 8 and following would be that what I am looking for. If there is something in a machine processable form (e.g. xml) this would be perfect. 

[1] https://www-ssl.intel.com/content/dam/www/public/us/en/documents/datashe... 

Unfortunately, there is no available formal documentation on these registers. We are looking into the possibility of providing this at a later date but it’s unlikely to be soon; due to other priorities, the document is necessarily further down on our list.

Oh, sad. Hope they are being released in a reasonable time frame.

Is there something something like an informal list / xml file containing the registers / offests / lengths / bitfields which we could use internally in our university?

No such documentation is available at this point in time. I have filed a Intel Premier Support Documentation Request ((#6000045270) on your behalf so that you can track this issue. 

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