I7 L3 cache replacement policy

I7 L3 cache replacement policy

I've found a blog article(http://blog.stuffedcow.net/2013/01/ivb-cache-replacement/) about Intel IvyBridge cache replacement policy. The blogger concluded that Ivy Bridge's L3 cache replacement policy is no longer pseudo-LRU.

Under the new cache replacement policy of Ivy Bridge, suppose that there are 4 sets in L3, and set 0 and 1 are using by a process. Set 2 and 3 are available to allocate. If a new process from other cpu tries to load two pages into L3 cache, is it guaranteed that the new process loads its pages into set 2 and 3? The addresses have the same index bits. In other words, if there are available cache sets in the last level cache, does HW always choose the available sets to load new pages?

1 post / 0 new
For more complete information about compiler optimizations, see our Optimization Notice.