IOAT DMA / Crystal Beach 3 Specifications

IOAT DMA / Crystal Beach 3 Specifications

Hi everyone,

I am looking for specifications for the Crystal Beach DMA controller. So far I only found the register specifications in the Xeon Processor Data sheet.

I've got a Ivy Bridge machine: Intel(R) Xeon(R) CPU E5-2670 v2 @ 2.50GHz running on an Intel Corporation C600/X79 series chipset.

We want to build a DMA driver for our research operating system (non Linux/Windows/solaris/bsd based). So I am basically looking for a specification to the following device i.e. how to setup the descriptor chains etc.

Intel Corporation Xeon E5 v2/Core i7 Crystal Beach DMA Channel 0 (rev 04)

Thanks, 
Reto

 

5 posts / 0 new
Last post
For more complete information about compiler optimizations, see our Optimization Notice.

I am also interested about the crystal beach DMA device.
I noticed that there is a 8-channel DMA device call crystal beach DMA and it is labeled as PCI device number 4( this doesn't matter).
My questions is :
1. What is this device used for? Normally, NICs, HDDs all have there independent bus mastering DMA engine. so what is this DMA engine intended for?
2. Can it be used to transfer data between memory locations? Can it address 32 bit address or 64 bit address?

Thank you in advance.

Citazione:

Fuwen Z. ha scritto:

1. What is this device used for? Normally, NICs, HDDs all have there independent bus mastering DMA engine. so what is this DMA engine intended for?

I have recently implemented a basic driver for our research operating system. However it's state is not complete and a bit more information would be useful.

What I have experienced so far, this device can be used for Memory-Memory transfers i.e. offloading the CPU memcpy. It also supports system memory to MMIO but not the other way round (which I cannot understand why)

Citazione:

Fuwen Z. ha scritto:

2. Can it be used to transfer data between memory locations? Can it address 32 bit address or 64 bit address

Yes, you can do various kind of transfers like xor, memcpy etc...  The addresses used are 64 bit.

 

I haven't got any good documentation about this. The Xeon Processor specification describes the registers. If you want to have a look at the functionality I recommend the linux driver for now. (included in the recent Linux Kernel)

Sample code to exercise the ioat engine is in the last place you'd look, the driver. There's a self-test routine which is a
perfect example of synchronous IO. http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/driv...

Just use dma_request_channel to get a chan like so

{
    dma_cap_mask_t   mask;
    struct dma_chan     *mychan;

    dma_cap_zero(mask);
    dma_cap_set(DMA_MEMCPY, mask);
    printk(KERN_INFO "requesting dma channel\n");

    mychan = dma_request_channel(mask, NULL, NULL);

    if (!mychan) {
        info("no channel available\n");
        goto out;
    }

    printk(KERN_INFO "got channel %d!\n", mychan->chan_id);
    
    //do dma

    dma_release_channel(mychan);

}

I hope this helps, I spent a lot of time in the dark on this :). DMA from iomem doesn't work for me, crashes the ioat driver. 

Leave a Comment

Please sign in to add a comment. Not a member? Join today