address spaces in protected-mode of Pentium

address spaces in protected-mode of Pentium


I would like to ask an question connected with the theory:
What are the three address spaces supported by Pentium in the protected-mode?

Please help

10x all

4 posts / 0 new
Last post
For more complete information about compiler optimizations, see our Optimization Notice.

Your question is very similar to an assignment in the book

Introduction to Assembly Language Programming: For Pentium and RISC Processors

By Sivarama P. Dandamudi

The exercise appears on page 65 and is exercise 3-2.

It also appears in the book

Fundamentals of Computer Organization and Design

By Sivarama P. Dandamudi

This exercise is on page 271 and is exercise 7-2.
You can go to to see the following:
What Mode of Addressing do the Intel Processors Use?


  • Address mode
  • Protected mode
  • Real mode
  • SMM mode
  • Virtual 8088 mode

Intel processors since the Intel386
processor can run one of three modes. They are the Real mode, Protected
mode and SMM mode. You can also add a forth mode called Virtual 8088
mode, which is considered a pseudo mode of the protected mode. When the
processor starts booting the computer, the processor starts in real
mode where it operates like a 8086 processor that can see up to 1 MB of
RAM. The native mode for the processor is the Protected mode which it
will switch into while it loads Windows* or some other advanced
operating system. While in protected mode, the processor uses segmented
(non-linear) addressing, as opposed to linear addressing. Segmented
addressing means that memory (physical memory and virtual memory) is
divided into 64K blocks. This is the maximum value for the Instruction
Pointer (IP) register. The IP register works with the Code Segment (CS)
register to point to the memory location from where the microprocessor
should fetch its next instruction. The IP uses 4 bytes for memory
addressing, therefore making 0FFFFH the maximum memory location (0FFFFH
= 64K). For more information, refer to the Intel Architecture Software Developer's Manual - Volume 1: Basic Architecture.

This applies to:

Dual-Core Intel Xeon Processor 7000 Sequence

Intel Celeron Processor Family

Intel Core Duo Processor

Intel Core Solo processor

Intel Core2 Duo Desktop Processor

Intel Core2 Duo Mobile Processor

Intel Core2 Extreme Processor

Intel Pentium 4 Processor

Intel Pentium
4 Processor Extreme Edition

Intel Pentium D Processor

Intel Pentium III Processor

Intel Pentium III Xeon Processor

Intel Pentium M Processor

Intel Pentium Processor Extreme Edition

Intel Xeon Processor

Mobile Intel Celeron Processors

Mobile Intel Pentium 4 Processors - M

Mobile Intel Pentium III Processors

Multi-Core Intel Xeon Processor 3000 Sequence

Multi-Core Intel Xeon Processor 5000 Sequence

I'm not shure and I want ot ask am I on the right way.
I think that the address spaces in protected mode are:
- I/O address space
- non-linear addressing space (segmetated, logical address space)
- linear address space (pagin traslation to phisical address, if no paging then linear = physical address)

Please tell me because i am not sure about my conclusion

The CPU uses two address spaces: I/O tocontrol devices on I/O ports,
and Memory forROM, DRAM, MMIOtransactions. You may have a third mixed
in there called Config space which is used to configure your PCI bus

Leave a Comment

Please sign in to add a comment. Not a member? Join today