UnDocumented MSR's

UnDocumented MSR's

I have come accross BIOS code that reads/writes an MSR ECX = 0x2e0.  I have scanned through all of the Intel documentation and cant find anything about this MSR

The codes is executed on a CORE i7 3820qm



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For more complete information about compiler optimizations, see our Optimization Notice.

You may want to check out the "Default x86 Port Address Assignments" table from this website:



I think the table above lists I/O ports, whereas the question was about MSRs.

MSR 0x2e0 seems to enable no-evict mode (NEM), also known as Cache-as-RAM which is used to execute the firmware code (BIOS/UEFI) for the early boot stage from the CPU's cache. Without Cache-as-RAM, code fetches are routed directly to the SPI flash that holds the firmware, which is painfully slow.

This StackOverflow answer has some useful details: http://stackoverflow.com/a/24710093/537046

Update 2: A 2011 Lenovo patent http://www.google.com/patents/US8037292 discusses using the newer (?) No-Eviction mode (NEM) on Intel CPUs for loading the BIOS in the CPU's cache. The method can probably be used for other type of code, including supervisors. There's a big caveat though. Code other than the already cached stuff will run very slowly, so I don't see this as really usable outside the boot procedure. There's some coreboot code showing how to enable NEM (https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/84defb44fabf2e81498c689d1b0713a479162fae/src/soc/intel/baytrail/romstage/cache_as_ram.inc)

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