The Intel Architecture Software Developers Manual has the following to say about
using PAE (Physical Address Extension) while in SMM (System Management Mode):
The physical address extension (PAE) mechanism introduced in the
P6 family processors is not supported when a processor is in SMM.
The IA-32e mode address-translation mechanism is not supported in
SMM. See Section 3.10 of Intel 64 and IA-32 Architectures
Software Developer's Manual, Volume 3A.
The addressable SMRAM address space ranges from 0 to FFFFFFFFH
(4 GBytes). (The physical address extension (enabled with the
PAE flag in control register CR4) is not supported in SMM.)
Yet, how is system firmware supposed to scrub ECC errors in high memory
(such as on the 5000P chipset) if this is true?
I have done a small amount of testing on PIII, P4 Xeon, and Core 2 processors
and found that I am able to set up PAE while in SMM and have tested access
to high memory beyond 4 GB by changing the appropriate page table entries.
Can Intel confirm whether the above text is still valid for current processors
or provide insight as to how we can scrub ECC correctables?