CPU Documentation Request

CPU Documentation Request

I need documentation on Core i7 integrated memory controller programming (PCI address space, configuration registers, etc -- the same level of documentation that was available for X38 MCH).

I am also wondering when will the updated developer's manualsand the AP-485 be available for download?

EDIT: I see that the Volumes 1 to 3 have been updated to 028. Got those.

AP-485 is still at 032, will that document be updated ever again or it can be considered deprecated?

The download page still hasthe samemistake I reported long timeago:

"The downloadable PDF of the Intel 64 and IA-32 Architectures Optimization Reference manual is at version 015"

It is at version 016, not 015.

Furthermore, said Optimization manual(produced by someone namedjdonato)still hasContent Copyingdisabled so thatone cannot copy example code out of the document which I also reported long ago.

As I said before, malicious people can always crack the PDF password, you are just inconveniencing developers for whom you made the document in the first place.

Lexi where are you, this "having to report every issue twice" is getting old.

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For more complete information about compiler optimizations, see our Optimization Notice.

Quoting - Igor Levicki

I need documentation on Core i7 integrated memory controller programming (PCI address space, configuration registers, etc -- the same level of documentation that was available for X38 MCH).

I am also wondering when will the updated developer's manualsand the AP-485 be available for download?

EDIT: I see that the Volumes 1 to 3 have been updated to 028. Got those.

AP-485 is still at 032, will that document be updated ever again or it can be considered deprecated?

The download page still hasthe samemistake I reported long timeago:

"The downloadable PDF of the Intel 64 and IA-32 Architectures Optimization Reference manual is at version 015"

It is at version 016, not 015.

Furthermore, said Optimization manual(produced by someone namedjdonato)still hasContent Copyingdisabled so thatone cannot copy example code out of the document which I also reported long ago.

As I said before, malicious people can always crack the PDF password, you are just inconveniencing developers for whom you made the document in the first place.

Lexi where are you, this "having to report every issue twice" is getting old.

I forward your question on X58 to data sheet owners.

You might have noticed that rev 29 of SDM has been published in November.

Rev 17 of the Optimization has been submitted to the web folks for publication, You should see rev 17 as soon as they get through the holiday hiatus. I believe you will see the incorrect permission setting corrected in rev 17.

Shihjong

Quoting - Shih Kuo (Intel)

I forward your question on X58 to data sheet owners.

You might have noticed that rev 29 of SDM has been published in November.

Rev 17 of the Optimization has been submitted to the web folks for publication, You should see rev 17 as soon as they get through the holiday hiatus. I believe you will see the incorrect permission setting corrected in rev 17.

Shihjong

Thank you.

Best Reply

Quoting - Igor Levicki

Thank you.

my colleague responded, you can download the data sheets

http://download.intel.com/design/processor/datashts/320835.pdf

and

http://www.intel.com/Assets/PDF/datasheet/320838.pdf

Shihjong

Quoting - Igor Levicki

Thank you.

The lateste Optimization manual is live

Quoting - Shih Kuo (Intel)

The lateste Optimization manual is live

Thank you!

There is one more documentation related query I have -- namely the X38/X48 MCH documentation doesn't have any references to register at address/offset 0x265. That is the register which holds the CAS (Column Address Strobe) value. I wonder if that is simply an oversight or it was omitted on purpose?

I am asking because a friend of mine who is new to Intel platform development is trying to write a utility similar to CPU-Z, and he can't find the information on all chipset registers he needs.

And while you're at it, the IPF documentation needs some heavy updating. I still see some obsolete information present in those documents, such as the IA-32 <> IA-64 instruction set modes, which are no longer present as of Montecito from what I remember. Will the documentation be updated now, when Tukzilla is released, or much later?

HiAdam,

Shih-jong kindly alerted me to yourquestion on this forumabout Itanium processor documentation.

With the dual-core Itanium processors, Intel introduced two different mechanisms to support IA-32 instruction execution.

1. PAL-based IA-32 execution is used to enable BIOS tohandle IA-32 instructions prior to OS boot. For example, an Itanium-based BIOS can use PAL-based IA-32 execution to support IA-32 option ROMs. When PAL-based IA-32 execution is running, PSR.is set to 1 to indicate that the IA-32 instruction set is running.

2. IA-32 Execution Layer is an OS-level optimizingbinary translator that allows operating systems such as Windows and Linux to run IA-32 applications. As far as the processor is concerned, there's no instruction set change when IA-32 Execution Layer is running,so PSR.isremains 0.

So, Itanium architecture continue to support PSR.is although the implementation is somewhat different with the dual-core Itanium processors.

David

Quoting - "David"

Hi Adam,

Shih-jong kindly alerted me to your question on this forum about Itanium processor documentation.

With the dual-core Itanium processors, Intel introduced two different mechanisms to support IA-32 instruction execution.

1. PAL-based IA-32 execution is used to enable BIOS to handle IA-32 instructions prior to OS boot. For example, an Itanium-based BIOS can use PAL-based IA-32 execution to support IA-32 option ROMs. When PAL-based IA-32 execution is running, PSR.is set to 1 to indicate that the IA-32 instruction set is running.

2. IA-32 Execution Layer is an OS-level optimizing binary translator that allows operating systems such as Windows and Linux to run IA-32 applications. As far as the processor is concerned, there's no instruction set change when IA-32 Execution Layer is running, so PSR.is remains 0.

So, Itanium architecture continue to support PSR.is although the implementation is somewhat different with the dual-core Itanium processors.

David

So does that mean that, for dual-core IA-64 processors, the PSR.is register is always 0 and writes to it are discarded? (or something like that anyway)

Also with regards to documentation; what about new instruction sets supported by the newer models, to take advantage of say some of the power management enhancements and utilization of multiple cores?

Adam,

I wonder have you ever heard of a term thread hijacking? What you are doing here is simply rude.

Yes I have heard about thread hijacking (very briefly though). And I wasn't trying to hijack your thread.

You may have received a reply that I was directing to David Song. Unfortunately, every time I click on "Reply to Post" it redirects me to some "cannot be found" page. I am unaware of how to report such bugs (every time I tried to report they thought I was spamming them and I would get a message reply via email saying this)

So I had to use the "Reply to Thread" button, and modify the existing quote that was already preset in the reply editor.

Adam,

This thread, although titled "CPU Documentation Request", is focused on X86 CPU family.

Your first interjection with Itanium was thus off-topic.

As if once wasn't enough you persisted in firing tangents off the main topic.

I ignored you the first time, asked another question, and I was expecting to get an answer since I am subscribed to this thread but instead of learning what I need to know I am wasting time reading your posts, and attempting to teach you some basic netiquette.

Sorry if I am being too blunt here, but I am trying to say that you should've started your own thread instead of hijacking mine. Hijacking is bad because:

1. You have to wait for someone to discover your post in a wrong thread and to be willing to continue off-topic discussion with you

2. By means of your off-topic post being the last one, the original poster risks not getting an answer to their last question unless repeated

3. Because of #2, it becomes harder for those who can help us to wade through our posts and find what has been answered and what hasn't, so they give up and we both don't get any answers

Please consider that for your future forum participation. Thank you.

As for the inability to use the Reply feature, I am experiencing that too so it must be some temporary forum issue.

First of all, thank you for pointing out that it was about x86 only (as you can tell my knowledge on x86 isn't really that great).

Like I previously mentioned; I wasn't trying to post an "off-topic" post. I thought the post was about "CPU Documentation" and so I posted a request for up-to-date documentation for the Itanium CPU. That was, until you explained me what you were talking about.

I wasn't expecting the exact response I got from David (I was expecting an "It's up to date now" type response). So at the same time that confused me as to whether I was supposed to ask my question or not.

As for netiquette: I never asked you to waste my time "teaching me about nettiquete". I suppose after going up the snakes and down the ladders on the Intel websites (in which decent documentation [other than "best enterprise solution ever" ads] is getting harder and harder to find from) I probably got a little impatient, so I apologize for any inconvenience I may have caused (I do hope I am able to make myself clear and that this is the last both of us will be seeing of this particular "argument").

Quoting - Adam Kachwalla

First of all, thank you for pointing out that it was about x86 only (as you can tell my knowledge on x86 isn't really that great).

Like I previously mentioned; I wasn't trying to post an "off-topic" post. I thought the post was about "CPU Documentation" and so I posted a request for up-to-date documentation for the Itanium CPU. That was, until you explained me what you were talking about.

I wasn't expecting the exact response I got from David (I was expecting an "It's up to date now" type response). So at the same time that confused me as to whether I was supposed to ask my question or not.

As for netiquette: I never asked you to waste my time "teaching me about nettiquete". I suppose after going up the snakes and down the ladders on the Intel websites (in which decent documentation [other than "best enterprise solution ever" ads] is getting harder and harder to find from) I probably got a little impatient, so I apologize for any inconvenience I may have caused (I do hope I am able to make myself clear and that this is the last both of us will be seeing of this particular "argument").

Well, just to make things clear from where I stand -- when dropping into someone's thread which at a glance has a topic similar to what you may have posted yourself, common courtesy implies that you at least read the original (i.e. the first) post if not the whole thread. That way you should be able to tell how related is what you have to say to what has already been said, and decide whether to start a new discussion or join the existing one.

Now if you were less centered on your own needs I wouldn't have to say a thing, but you left me with no choice.

What you did is akin to seeing two people whom you don't know discuss something at a party, and then rudely interrupting them with a similar yet unrelated topic of yours without introducing yourself, and without waiting for them to finish the conversation. I am pretty sure you would find such behavior annoying as well if someone did that to you.

Furthermore, if you are a registered developer (i.e. you have Premier account) and if your documentation request was urgent you could have opened a new issue or emailed developer support and got the reply much sooner so impatience is a rather poor excuse.

As for the apology, I haven't asked for one -- I just wanted you to be mindfull of others in the future, that's all.

Quoting - Adam Kachwalla

So does that mean that, for dual-core IA-64 processors, the PSR.is register is always 0 and writes to it are discarded? (or something like that anyway)

Also with regards to documentation; what about new instruction sets supported by the newer models, to take advantage of say some of the power management enhancements and utilization of multiple cores?

Hi Adam,

Let me respond to your follow-up questions here. If you have further questions, could you start a separate thread?

Hardware will flip the PSR.is bit when software invokes an instruction set transaction through the rfi, br.ia, or jmpe instructions. If BIOS decides to transition to IA-32 execution (e.g., to support an IA-32 option ROM), PAL-based IA-32 execution is invoked and PSR.is will be set to 1.

When IA-32 applications are running on IA-32 Execution Layer, PSR.is remains cleared to 0.

We published some architectural changes to support variable-frequency mode and ACPI P-state clarifications in the Intel Itanium Archtiecture Software Developer's Manual Specification Update, June 2008 available at: http://www.intel.com/design/itanium/documentation.htm?=Itanium+tab_technical_docs.

Regarding multiple hardware threads (or logical processors) running on the same core, Itanium SDM 2.2 documents the "hint @pause" instruction, which lets software indicate to hardware that the thread is spin-looping or doing some other low priority task. SDM 2.2 also documents PAL_LOGICAL_TO_PHYSICAL, which allows system software to determine the logical processor and cache hierarchy in the processor.

I hope that's helpful. Is there some other functionality you're looking for?

David

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