invalid pci read operation on a burst of writes

invalid pci read operation on a burst of writes

The test I am using writes data from a write combined mapped memory to a prefetch window in the board's address space. With a pci analyzer, a read transaction appears in the application buffer zone. The read does not occur at the same place. Sometimes, before the read, the analyzer records a special transaction. The read operation fetches 4 bytes always. In software, there are no reads taking place. Can anyone explain this?

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Hi Caliniaru,

Thisis more the province of Intel's chipset design groups -- if you do not receive the answer you're looking for in the community and you aredoing your development work through a company,we recommend working withan Intel Product Representative.

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