Can someone descripe how DDR2 memory manages its distribution ?
Just like why the memory is divided into 0000_0000h~0x0000F4 or others ?
Could someone help me to understand in this regard ?
This is outside the scope of what the Intel Software Network handles -- the topic is mentioned tangentially in some of the chipset documentation on the Intel Hardware Design site, but probably not at the depth you're looking for.
If you work for a company that has an assigned Intel rep, or that works with an FAE contact at an Intel Authorized Distributor, you can try requesting support via that channel. Beyond that, we recommend searching sites specializing in hardware design issues.
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