I found an interesting masters thesis by Robert Martin online called "Multi-Level Cell Flash Memnory Fault Testing and Diagnosis". It applied to both single bit flash and multi-bit NOR flash architectures. The biggest problem with the thesis from my perspective is that detailed knowledge of the internal row/column architecture is need to perform the diagonal test pattern iterations. It also mentioned programming each cell to every "11", "10", "01", and "00" state. From an external interface, I can see no way to do this.
I can find no official white paper, or application note describing a suitable power on, or manufacturing test strategy for testing flash memory. SDRAM marching test patterns are not sufficient. When I was at Cabletron/Enterasys we did have a three pass algorithm to test flash but since I have moved on to another firm I cannot get access to this source code. I never did find the basis for the patterns used by that test. If someone from the Flash products group in Folsom CA can point me to a fairly universal algorithm, or some method of using the CFI interface to implement the diagonal testing method mentioned above, it would be appreciated.