Am trying to design an Xscale board (PXA255) with 256Mbyte SDRAM, but it appears that the Xscale architecture doesn't support the higher density SDRAMs that are available today. Could I use the 512Mbit (16-bit wide) chips from Samsung, which have 4 internal banks, in such a way that two of these chips together would give me a 32-bit wide memory block of 128Mbyte?
This violates the stipulation that each partition can have only 64Mbyte. Or maybe not. Could I consider that the lower two banks of this chip pair give me 64Mbytes in Partition 0 and the higher two banks of the pair give me 64MB in Partition 1? And then a second pair would similarly give me Partitions 2 &3...
If that is conceptually possible, then we get into the nitty gritty of the number of row and column lines and the bank selects, and whether the Xscale architecture can make use of this chip (Samsung's K4S511632) which needs 2 bank select lines, 13 row addresses and 10 column addresses. How does one handle the division of Chip-Select? I can add a fast logic chip that will translate chip-select signals from the processorinto appropriate chip-selects for the two pairs, and also manipulate the bank-select inputs based on the CS signals.
Do you have any idea whether this workable? Have the brains at Intel got a solution up their sleeves? Or on the other hand, do they know for sure this won't work?
Or do I just have to work this out on my ageing biological CPU and hope it hasn't got logic corruption?
Any (relevant) advice will be much appreciated!
P.S. I want to avoid creating a board with 8 lower-density RAM chips because of the signal integrity problems that would accompany it.