Can someone clarify the difference in intent (not effect) between ignored and reserved Itanium registers?
We are forwarding your question to our engineering contacts and will let you know how they respond.
Message Edited by intel.software.network.support on 12-02-2005 01:15 PM
Here is the response we received from our engineering contacts:
The technical documentation for the Intel Itanium architecture is very clear about "reserved" and "ignored" fields/registers. There is a section in Chapter 3 of the Intel Itanium Architecture Software Developer's Manual, Volume 1: Application Architecture, that describes this. Also, please refer to the legal text at the beginning of the manual:Designers must not rely on the absence or characteristics of any features marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Our engineers' understanding of your question is closer to the following: Why does the Intel Itanium architecture have ignored registers (i.e. why are they not all reserved)? This mainly applies to the application register set where AR 48-63 and AR 112-127 are ignored versus reserved.
The intent for ignored registers is to provide backward compatibility for application registers that Intel has not yet implemented in todays processors, but may implement at some point in the future. For example, if a new AR were to be implemented on a future version of the Itanium processor at AR48, without the previously ignored register, the OS would have to save and restore this new register during context switches, changing the amount of memory required for reads and writes during the context switch. With this register ignored by earlier versions of the Itanium processor, the size of memory required for a context switch remains the same for future versions which implement some functionality for it. Thus, the exact same OS code could run without modification on past, current, and future processors, regardless of whether they implemented the new register or not. With reserved registers, the same code would not work across generations since any access to a reserved register creates a fault.
We hope this is helpful.
Message Edited by intel.software.network.support on 12-02-2005 01:16 PM
Based on this rationale, why are any registers reserved? If the reserved registers were to be defined in some future implementation, then code that accesses these registers would fault on older implementations.
If an application register would be implemenented in future Itaniums for new functionality, would it be a currently reserved or ignored register?
Our engineering contacts replied:
Registers are reserved to prevent user-level applications from using them as temporary storage for data values. Only the minimum required number of registers are reserved to keep the memory required for a context switch at a minimum. Once a register has been reserved, it will remain reserved in all future implementations to prevent faults of the exact same type that you refer to. Ignored registers are explicitly ignored so that no application can gain any benefit from their use. Therefore, programmers have no incentive to use those registers for any reason. Accessing them is simply a waste of time and space in the program. A future processor may then implement a new reserved register (which was previously ignored) with the assurance that no legacy applications will fault by accessing the previously ignored register. Updated BIOS and OS versions will then be able to correctly support the new processor.
New functionality may be implemented either as a new reserved register (which was previously ignored), or as a previously unused field of a previously reserved register.