EOF for Shared Bus Architecture?

EOF for Shared Bus Architecture?

Last 2 years of Intel in single CPU space were not too bad. Hyperthreading, faster FSB, SSE3 etc.
But what about Dual and Quad CPU x86 systems ?
How long Intel will be sitting on shared bus architecture? It is really major problem, and no amount of cache on Xeon CPUs or FSB speedup is going to solve it. Hypertransport is flourishing meanwhile on multi-CPU IBM/Apple and AMD systems.
So, where is Intel going with shared bus/memory architecture? Will we be it the same place 2 years from now?
Cmon time to make some changes. Good CPUs need good memory bus.
I hope Im missing something, but I dont see how shared (memory) bus will do it anymore.

Thank you,
at

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Hi Alex,

Thanks for your feedback.

For publicly posted information on R&D at Intel, please visit: http://www.intel.com/research/

You might be specifically interested in the Computing Platforms pages:
http://www.intel.com/labs/hardware/

Beyond that, as a general corporate policy, the technical support staff is unable to comment on unannounced Intel products, future technologies or technology trends. When new technologies are released, information concerning them can be accessed through the URL http://developer.intel.com/design/product.htm, or through the Intel Press Room site at: www.intel.com/pressroom/

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

Message Edited by intel.software.network.support on 12-07-2005 04:36 PM

Lexi, thank you for the reply.

Ive looked at the pages provided, and googled the issue on Intel for NUMA. There is nothing recent, beyond SGI NUMA for Itanium, which is not x86 architecture. I understand Intel internal policy, but really there is no even definite roadmap for Xeon for now.
I strongly believe that Intel is making another big mistake by ignoring NUMA for Xeon systems. It is already issue for now days high performance application, and will be showstopper a year from now.

at

Hi Alex,

We forwarded your question to ourcontact within our Enterprise Platforms Group. Here is their response:

Today Intel offers processors in the 2-way, 4-way and>4-way space that utilize a shared bus architecture. Recently, Intel launched the new Intel Xeon processor 2-way design based on a chipset codenamed "Lindenhurst". This new platform brought several advances to the shared bus architecture including a faster 800MHz front side bus (for improved bandwidth), DDR II memory running at 400MHz (for faster memory accesses and improved memory performance) and PCI-Express technology (for dramatically faster I/O). We are the only manufacturer offering these technologies andtheindustry-leading performance of these new Intel Xeon 2-way boxes proves that there is plenty of headroom left in a shared bus architecture. Weare already sampling4-way platforms withsimilar advances in them and we will continue to make improvements to our Intel Xeon processor DP and Intel Xeon Processor MP platforms over time.

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

Message Edited by intel.software.network.support on 12-02-2005 08:49 PM

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