I wanted to experiment with DVFS on Intel SandyBridge and through the Intel Manual 3B, I see that the DVFS is achieved on SandyBridge using Enhanced Intel SpeedStep.
It says that IA32_PERF_CTL could be set to achieve DVFS. However the Manual does not explain how to set the lower 16 bits in IA32_PERF_CTL to achieve this. I went across searching on different forums to ascertain how to set this to no avail. However, what I could learn is that the 16 bits are divided into two 8-bit blocks that specify the Multiplier and VID.
I also found that the multiplier can be found on intel sandy bridge as
- [CPU frequency] = BCLK x [CPU multiplier].
I am using a Xeon E5-2680 with 2.7GHz. The data sheet says the BCLK0 and BCLK1 are 100MHz(Table:6-11).
So the current multiplier seems to be 27.
The VID range is 0.60V-1.35V.
1. Now if I have to scale the frequency, do the go about changing 8-MSB(15-8) to any value lesser than 27 only?
2. Or do I need to change the 8-LSB(7-0) between 0.6 and 1.35V.
I am aware that SandyBridge has a limited set of P-states from P0 to PN and I just can't go about setting the 16-bits as per my will.
So, What I basically wanna know is how do I do DVFS on SandyBridge?
PS: Please correct me if my understanding so far is incorrect.
Thanks in advance.