Local (CPU) APIC address?

Local (CPU) APIC address?



I was reading the "Desktop 4th Generation Intel® Core™Processor Family" Datasheet at https://www-ssl.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-desktop-vol-2-datasheet.pdf


...and it shows the Local (CPU) APIC address to be at FEC80000h -



But then underneath it says the following -


"Memory requests to this range would then be forwarded to the PCI Express* port. This mode is intended for the entry Workstation/Server SKU of the PCH, and would be disabled in typical Desktop systems. When disabled, any access within the entire APIC Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI."


This contradicts what the image shows and suggested that FEC0_0000h to FECF_FFFFh will go to the DMI to the I/O Apic.


I have checked the MADT tables and it shows the local CPU address to be FEE0_0000, which it is on most systems. This then clashes with what is shown to be MSI interrupts.


2 questions then really,


Do both the local CPU APIC and MSI interrupts use FEE0_0000h?


What is this range between FEC8_0000h - FECF_FFFF for?


My CPU is the Core i5 4570 on the Z87 chipset.


Any help would be appreciated.


Kind Regards,

Robert Smith

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Any help clearing this up would be appreciated.


Hi Robert,

You might try the processor community if you have not already done so.


You can also send an email directly to processor support from here: 


Regards, Hal G

Intel(R) Developer Zone Support

*Other names and brands may be claimed as the property of others.









Thanks Hal,

I've sent an E-mail to Processor support.

Kind Regards,


Are you using Linux or Windows?

Hi liyapolak,

I am on Windows 7


>>>What is this range between FEC8_0000h - FECF_FFFF for?>>>

Did you try to check with the windbg  quoted address range?


I think I've figured it out.

The Haswell datasheet says "The processor optionally supports additional I/O APICs behind the PCI Express* “Graphics” port. When enabled using the APIC_BASE and APIC_LIMIT registers (mapped PCI Express* Configuration space offset 240h and 244h), the PCI Express*
port(s) will positively decode a subset of the APIC configuration space."

Looking back at older datasheets the area between FEC8_0000 and FECF_FFFF is called the 'PCI Express IO APIC space'.

As the PCI Express ports are in the physical CPU in newer CPUs it is listed as a 'local (CPU) APIC' address range and is nothing to do with the local APIC and MSI range at FEE0_0000.

Thanks for the help,


You are welcome.

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