Workshops


Learn the basics of designing custom logic on Intel® FPGA technology with these project-based workshops. Each workshop contains lecture slides plus multiple labs and exercises designed for new users. To be successful, first read or watch the lecture material, and then complete the associated projects.

Required Software

Intel® Quartus® Prime Software

The lite edition is free to all users.

System and Software Requirements

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Note For faster download times, select only the device support package that you need. Average download times are 30-60 minutes.

Required Hardware

Laptop or desktop computer with USB port

An Intel® FPGA Development Kit

Students and professors can receive an academic discount through our partner, Terasic.

Purchase

Note Workshops are based on the Terasic DE10-Lite but can be adapted for other Intel FPGA Development Kits with similar features, unless stated otherwise.

Introduction to FPGA Design in Intel® Quartus® Prime Software

Explore the features of Intel Quartus software through the creation of simple FPGA designs. Learn how FPGAs work and write Verilog code to implement your first custom logic project.

Prerequisites: Boolean algebra, combinational logic, sequential logic, basic coding

Download Materials   Lecture Recording


Embedded FPGA Design Using the Nios® II Processor

Use Platform Designer to build a customized embedded system using a soft processor. Write bare-metal software using the open source Eclipse* IDE. Interact with an I/O peripheral using functions from the Nios II Hardware Abstraction Layer (HAL).

Prerequisites: Computer organization, software development in C

Download Materials   Lecture Recording


Introduction to Static Timing Analysis of Digital Circuits

Calculate timing margins by completing paper and pencil exercises. Practice writing, analyzing, and correcting constraints using the Timing Analysis tool within the Intel Quartus Prime Software Suite.

Prerequisites: Digital logic design, computer architecture

Download Materials   Lecture Recording

 


Introduction to FPGA Simulation and Debug

Learn how to simulate and debug digital designs. Practice debugging real systems using tools in the Intel Quartus Prime Software Suite, such as ModelSim*, SignalTap, System Console, and In-System Sources and Probes Editor.

Prerequisites: Timing analysis

Download Materials   Lecture Recording


Introduction to High-Speed I/O

Learn about the importance of high-speed serializer and deserializer transceiver circuits by configuring, assembling, simulating, and testing your own transceiver bidirectional channel.

Prerequisites: Digital logic design, computer architecture

Note This workshop requires specialty transceiver hardware not found in the Terasic DE10-Lite, Terasic DE10-Nano, or Terasic DE1-SoC kits. We recommend the Cyclone® V FPGA GX Starter Kit from Terasic.

Purchase Cyclone V FPGA GX Starter Kit

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Introduction to Video

Explore VGA hardware to discover how video is stored, displayed, and formatted. Take that knowledge and use it to build a simple game.

Prerequisites: Digital logic design, computer architecture, Verilog, or VHDL

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Introduction to Memory

Use internal and external memory structures to build an efficient design. Configure, assemble, and benchmark on-chip dual port RAM, single port ROM, and external SDRAM.

Prerequisites: Digital logic design, computer architecture, Verilog, or VHDL

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Introduction to High-Level Design

Learn how to use C derivatives, such as OpenCL™ software technology and the Intel® High Level Synthesis Compiler, to describe FPGA designs without hardware description languages. Discover how to increase your productivity by building a computationally rich workload using Intel Quartus software, ModelSim, and the Intel® HLS Compiler.

Prerequisites: Digital logic design, computer architecture, coding in C and C++

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Introduction to FPGA Acceleration

Learn how to develop and deploy FPGAs for workload optimization in data center and cloud environments using the acceleration stack for Intel® Xeon® CPU with FPGAs. Practice writing host code that communicates transparently with the FPGA accelerator using the Open Programmable Acceleration Engine (OPAE).

Prerequisites: Coding in C and C++

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