The Hardware Accelerator Research Program is a global program that provides faculty and researchers early access to preproduction Intel® Xeon® processors with in-package field-programmable gate array (FPGA) systems.

This program is spurring research in programming tools, operating systems, and innovative applications for accelerator-based computing systems.

The program also offers tutorials, workshops, technical support, community forums, and opportunities for participants to showcase their research and results.

THE TECHNOLOGY

This reconfigurable hardware connects the Intel® Xeon® processor with an in-package FPGA via the platform’s high-speed Intel® QuickPath Interconnect (Intel® QPI), which improves system bandwidth.

The FPGA can be programmed to serve as a workload-optimized accelerator offering substantial performance, agility, and energy-efficiency advantages across many data center-type workloads.

The platform is also an ideal experimentation platform for innovative operating systems or computing systems research that focuses on novel approaches of integrating CPUs with accelerators at the software and hardware level.

Workloads

  • Cloud services
  • Analytics
  • Genomics
  • Security
  • Packet processing
  • Virtual switching
  • Compression
  • Deduplication

Application Domains

  • Machine learning
  • Data encryption
  • Compression
  • Image processing
  • Video-stream processing

CENTERS

Intel has partnered with the following centers to host a multinode computer cluster that uses the Intel® Xeon® processor packaged with the Intel® Arria® 10 FPGA.

Texas Advanced Computing Center (TACC)

TACC designs and deploys the world’s most powerful advanced computing technologies and innovative software solutions to enable researchers to answer complex questions and advance science and society.

Paderborn Center for Parallel Computing (PC²)

The Paderborn Center for Parallel Computing (PC²) is a scientific institute of Paderborn University, Germany. PC² operates several high-performance cluster systems with up to 10,000 cores to support researchers in computational sciences at Paderborn University and in North Rhine-Westfalia. This center strives to advance interdisciplinary research in parallel and distributed computing with innovative computer systems.

WORKSHOPS

Image of a hand holding a  Intel(r)  Xeon(r) Scalable Processor

Learn and Use the Intel® Xeon® Scalable Processor with an In-Package FPGA

This full-day workshop provides an overview of how to program the Intel® Xeon® Scalable processor with an in-package FPGA. The workshop also highlights Intel’s Hardware Accelerator Research Program. Learn about the hardware and software architecture, as well as how to program it using register transfer level (RTL) and OpenCL™ platform. A multihour hands-on lab session allows attendees to get direct experience on this exciting new technology.

Topics:

  • Overview of the Intel® Xeon® Scalable processor with in-package FPGA hardware and software architecture
  • Accelerator abstraction layer
  • Core cache interface and accelerator function unit design
  • Memory protocol factory
  • OpenCL programs
  • High-level design (HLD) methodology
  • Hands-on labs


Prerequisites: Basic knowledge of computer logic design and FPGA fundamentals

APPLY

Submit a proposal to join the program and get access to the Intel® Xeon® processor with an in-package FPGA.

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