Intel® Developer Zone:
Intel Instruction Set Architecture Extensions

Intel’s Instruction Set Architecture (ISA) continues to evolve to improve functionality, performance and the user experience. Featured below are planned extensions to the ISA that are new as well as those being planned for enhancements in future generations of processors. By publishing these extensions early, Intel helps ensure that the software ecosystem has time to innovate and come to market with enhanced and new products when the processors are launched.

Overview

Tools & Downloads

  • Intel® C++ Compiler

    The Intel® C++ Compiler is available for download from the Intel® Registration Center for all licensed customers. Evaluation versions of Intel® Software Development Products are also available for free download.

  • Intel Intrinsics Guide

    The Intel Intrinsics Guide is an interactive reference tool for Intel intrinsic instructions, which are C style functions that provide access to many Intel instructions – including Intel® Streaming SIMD Extensions (Intel® SSE), Intel® Advanced Vector Extensions (Intel® AVX), and more – without the need to write assembly code.

Intel® Advanced Vector Extensions (Intel® AVX)

The need for greater computing performance continues to grow across industry segments. To support rising demand and evolving usage models, we continue our history of innovation with the Intel® Advanced Vector Extensions (Intel® AVX) in products today.

Intel® AVX is a new-256 bit instruction set extension to Intel® SSE and is designed for applications that are Floating Point (FP) intensive. It was released early 2011 as part of the Intel® microarchitecture code name Sandy Bridge processor family and is present in platforms ranging from notebooks to servers. Intel AVX improves performance due to wider vectors, new extensible syntax, and rich functionality. This results in better management of data and general purpose applications like image, audio/video processing, scientific simulations, financial analytics and 3D modeling and analysis.

Intel® Advanced Vector Extensions 512 (Intel® AVX-512)

In the future, some new products will feature a significant leap to 512-bit SIMD support. Programs can pack eight double precision and sixteen single precision floating numbers within the 512-bit vectors, as well as eight 64-bit and sixteen 32-bit integers. This enables processing of twice the number of data elements that IntelAVX/AVX2 can process with a single instruction and four times the capabilities of Intel SSE.

Intel AVX-512 instructions are important because they open up higher performance capabilities for the most demanding computational tasks. Intel AVX-512 instructions offer the highest degree of compiler support by including an unprecedented level of richness in the design of the instruction capabilities.

Intel AVX-512 features include 32 vector registers each 512-bit wide and eight dedicated mask registers. Intel AVX-512 is a flexible instruction set that includes support for broadcast, embedded masking to enable predication, embedded floating point rounding control, embedded floating-point fault suppression, scatter instructions, high speed math instructions, and compact representation of large displacement values.

Intel AVX-512 offers a level of compatibility with Intel AVX which is stronger than prior transitions to new widths for SIMD operations. Unlike Intel SSE and Intel AVX which cannot be mixed without performance penalties, the mixing of Intel AVX and Intel AVX-512 instructions is supported without penalty. Intel AVX registers YMM0–YMM15 map into Intel AVX-512 registers ZMM0–ZMM15 (in x86-64 mode), very much like Intel SSE registers map into Intel AVX registers. Therefore, in processors with Intel AVX-512 support, Intel AVX and Intel AVX2 instructions operate on the lower 128 or 256 bits of the first 16 ZMM registers.

More information about the details about Intel AVX-512 instructions can be found in the blog "AVX-512 Instructions". The instructions are documented in the Intel® Architecture Instruction Set Extensions Programming Reference (see the "Overview" tab on this page).

Intel® System Studio - Solutions, Tips and Tricks
By robert-mueller-albrecht (Intel)Posted 12/03/20130
Training Slides Link to Training Slides Overview New Features and Components of Intel System Studio 2014 Detailed Overview of all Intel System Studio 2014 Components System Requirements Support Matrix - Full list of component support based on Host/Target OS and Embedded Platfo...
Installation of Intel® System Studio on Windows* Host
By Naveen Gv (Intel)Posted 10/07/20130
How to get Intel System Studio 2014 - Windows* Host package? Upon registering for the program you will receive a serial number and email with a license file. You will need either of these two to complete the installation process. If you want to use the license file you can point to it during ins...
How to install Intel® System Studio on Windows* OS
By adminPosted 10/06/20130
Topic: - How to install Intel® System Studio 2014 on Windows* OS Objective: - This article is focused on explaining step wise as “How to install Intel® System Studio 2014 on Windows* OS”. Installation: - After downloading Intel® System Studio 2014 – Windows* Host from Intel® registration center...
Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview
By Sreelekshmy Syamalakumari (Intel)Posted 10/04/20133
Download Article Intel® Xeon® Processor E5-2600 V2 Product Family Technical Overview [PDF 780KB] Contents Executive Summary Introduction Intel Xeon processor E5-2600 V2 product family enhancements Intel® Secure Key (DRNG) Intel® OS Guard (SMEP) Intel® Advanced Vector Extensions (Intel® AVX): Floa...

Pages

Subscribe to
The Chronicles of Phi - part 5 - Plesiochronous phasing barrier – tiled_HT3
By jimdempseyatthecovePosted 03/25/20141
For the next optimization, I knew what I wanted to do; I just didn’t know what to call it. In looking for words that describes loosely-synchronous, I came across plesiochronous: In telecommunications, a plesiochronous system is one where different parts of the system are almost, but not quite, p...
BKMs on the use of the SIMD directive
By Taylor Kidd (Intel)Posted 03/25/20140
We had an ask from one of the various “Birds of a Feather” meetings Intel® holds at venues such as at the Super Computing* (SC) and International Super Computing* (ISC) conferences. The customer wanted to know BKMs (Best Known Methods) on the proper usage of the new OpenMP* 4.0 / Intel® Cilk™ Plu...
The Chronicles of Phi - part 4 - Hyper-Thread Phalanx – tiled_HT2
By jimdempseyatthecovePosted 03/24/20140
The prior part (3) of this blog showed the effects of the first-level implementation of the Hyper-Thread Phalanx. The change in programming yielded 9.7% improvement in performance for the small model, and little to no improvement in the large model. This left part 3 of this blog with the question...
The Chronicles of Phi - part 3 Hyper-Thread Phalanx – tiled_HT1 continued
By jimdempseyatthecovePosted 03/12/20140
The prior part (2) of this blog provided a header and set of function that can be used to determine the logical core and logical Hyper-Thread number within the core. This determination is to be use in an optimization strategy called the Hyper-Thread Phalanx. The term phalanx is derived from a mi...

Pages

Subscribe to Intel Developer Zone Blogs

    Intel® Software Guard Extensions (Intel® SGX)

    Intel Vision Statement

    Computing workloads today are increasing in complexity, with hundreds of software modules delivered by different teams scattered across the world. Isolation of workloads on open platforms has been an ongoing effort, beginning with protected mode architecture to create a privilege separation between operating systems and applications. Recent malware attacks however have demonstrated the ability to penetrate into highly privileged modes and gain control over all the software on a platform.

    Intel® Software Guard Extensions (Intel® SGX) is a name for Intel Architecture extensions designed to increase the security of software through an “inverse sandbox” mechanism. In this approach, rather than attempting to identify and isolate all the malware on the platform, legitimate software can be sealed inside an enclave and protected from attack by the malware, irrespective of the privilege level of the latter. This would complement the ongoing efforts in securing the platform from malware intrusion, similar to how we install safes in our homes to protect valuables even while introducing more sophisticated locking and alarm systems to prevent and catch intruders.

    Getting Started (common to all ISA)

    Overview

    Tools & Downloads

    • No change to existing content

    Technical Content

    Intel® SGX for Dummies (Intel® SGX Design Objectives)
    By Matthew Hoekstra (Intel)Posted 09/26/20133
    Today the Intel® Software Guard Extensions (Intel® SGX) programming reference manual was published (more information is available here).  Given the significant time and effort that my colleagues and I have spent defining Intel® SGX, I can't find a strong enough word in my thesaurus to describe ho...
    Attestation & Sealing with Software Guard Extensions
    By Simon Johnson (Intel)Posted 09/18/20130
    Once you have instantiated a secured software environment (known as an enclave) with the new instructions from the Intel(r) Software Guard Extensions (SGX) you are now ready to load secrets into it for processing and storing on the platform. This is the purpose of the attestation and sealing feat...
    Subscribe to Intel Developer Zone Blogs
    Innovative Technology for CPU Based Attestation and Sealing
    By adminPosted 08/14/20130
    Download white paper as PDF By:Ittai Anati, Shay Gueron, Simon P Johnson, Vincent R Scarlata Intel Corporation Abstract Intel is developing the Intel® Software Guard Extensions (Intel® SGX) technology, an extension to Intel® Architecture for generating protected software containers. The container...
    Using Innovative Instructions to Create Trustworthy Software Solutions
    By adminPosted 08/14/20130
    Download white paper as PDF By:Matthew Hoekstra, Reshma Lal, Pradeep Pappachan, Carlos Rozas, Vinay Phegade, Juan del Cuvillo Intel Corporation Abstract Software developers face a number of challenges when creating applications that attempt to keep important data confidential. Even diligent use o...
    Innovative Instructions and Software Model for Isolated Execution
    By adminPosted 08/14/20130
    Download white paper as PDF By:Frank McKeen, Ilya Alexandrovich, Alex Berenzon, Carlos Rozas, Hisham Shafi, Vedvyas Shanbhogue and Uday SavagaonkarIntel Corporation Abstract For years the PC community has struggled to provide secure solutions on open platforms. Intel has developed innovative new ...
    Subscribe to

    Intel® Memory Protection Extensions (Intel® MPX)

    Computer systems face malicious attacks of increasing sophistication, and one of the more commonly observed forms is to cause or exploit buffer overruns (or overflows) in software applications.

    Intel® Memory Protection Extensions (Intel® MPX) is a name for Intel Architecture extensions designed to increase robustness of software. Intel MPX will provide hardware features that can be used in conjunction with compiler changes to check that memory references intended at compile time do not become unsafe at runtime. Two of the most important goals of Intel MPX are to provide this capability at low overhead for newly compiled code, and to provide compatibility mechanisms with legacy software components. Intel MPX will be available in a future Intel® processor.

    Using Intel® SDE's chip-check feature
    By Mark Charney (Intel)Posted 10/03/20130
    Intel® SDE includes a software validation mechanism to restrict executed instructions to a particular microprocessor. This is intended to be a helpful diagnostic tool for use when deploying new software. Use chip check when you want to make sure that your program is not using instruction features...
    Using Intel® MPX with the Intel® Software Development Emulator
    By Ady Tal (Intel)Posted 07/23/20130
    Intel has announced a new technology called Intel® Memory Protection Extensions (Intel® MPX). To find out more, check out the Instruction Set Extensions web pages.  Once you know about Intel MPX, you may want to experiment with Intel® SDE. This article explains how to run Intel MPX with Intel SDE...
    Linux* ABI
    By Milind Girkar (Intel)Posted 07/18/20130
    by Milind Girkar, Hongjiu Lu, David Kreitzer, and Vyacheslav Zakharin (Intel) Description of the Intel® AVX, Intel® AVX2, Intel® AVX-512 and Intel® MPX extensions required for the Intel® 64 architecture application binary interface.
    Introduction to Intel® Memory Protection Extensions
    By RB (Intel)Posted 07/16/20130
    The C and C++ languages provide for memory access via pointers, however, these languages do not ensure the safe use of pointers. Left undetected, the unsafe use of pointers puts an application at risk of data corruption or malicious attack via buffer overruns and overflows. Intel is always lookin...

    Pages

    Subscribe to
    Intel® Memory Protection Extensions (Intel® MPX) Runtime Support
    By Brian Vajda (Intel)Posted 07/23/20130
    Enabling an application to use Intel MPX will generally not require source code updates but there is some runtime code needed in order to make use of Intel MPX.  For most applications this runtime support will be available by linking to a library supplied by the compiler or possibly it will come ...
    Intel® Memory Protection Extensions (Intel® MPX) Design Considerations
    By Baiju Patel. (Intel)Posted 07/23/20130
    My very first exposure to buffer overflow was with Morris worm in 80’s and since then, we collectively have tried to get a good handle on buffer overflow as it impacts both security and robustness of C/C++ software. Needless to say, we have made significant progress with addressing buffer overfl...
    Intel® Memory Protection Extensions (Intel® MPX) support in the GNU toolchain
    By Igor Zamyatin (Intel)Posted 07/22/20130
    Invalid memory access problem is commonly found in many C/C++ programs and leads to time consuming debugging, program instability and vulnerability. Many attacks exploit software bugs related to inappropriate memory accesses caused by buffer overflow (or buffer overruns). Existing set of techniq...
    Subscribe to Intel Developer Zone Blogs

      Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)

      The Secure Hash Algorithm (SHA) is one of the most commonly employed cryptographic algorithms.  Primary usages of SHA include data integrity, message authentication, digital signatures, and data de-duplication.  As the pervasive use of security solutions continues to grow, SHA can be seen in more applications now than ever. The Intel® SHA Extensions are designed to improve the performance of these compute intensive algorithms on Intel® architecture-based processors.

      The Intel® SHA Extensions are a family of seven Intel® Streaming SIMD Extensions (Intel® SSE)-based instructions that are used together to accelerate the performance of processing SHA-1 and SHA-256 on Intel architecture-based processors.  Given the growing importance of SHA in our everyday computing devices, the new instructions are designed to provide a needed boost of performance to hashing a single buffer of data. The performance benefits will not only help improve responsiveness and lower power consumption for a given application, they may enable developers to adopt SHA in new applications to protect data while delivering to their user experience goals. The instructions are defined in a way that simplifies their mapping into the algorithm processing flow of most software libraries, thus enabling easier development.

      Innovative Technology for CPU Based Attestation and Sealing
      By adminPosted 08/14/20130
      Download white paper as PDF By:Ittai Anati, Shay Gueron, Simon P Johnson, Vincent R Scarlata Intel Corporation Abstract Intel is developing the Intel® Software Guard Extensions (Intel® SGX) technology, an extension to Intel® Architecture for generating protected software containers. The container...
      Using Innovative Instructions to Create Trustworthy Software Solutions
      By adminPosted 08/14/20130
      Download white paper as PDF By:Matthew Hoekstra, Reshma Lal, Pradeep Pappachan, Carlos Rozas, Vinay Phegade, Juan del Cuvillo Intel Corporation Abstract Software developers face a number of challenges when creating applications that attempt to keep important data confidential. Even diligent use o...
      Innovative Instructions and Software Model for Isolated Execution
      By adminPosted 08/14/20130
      Download white paper as PDF By:Frank McKeen, Ilya Alexandrovich, Alex Berenzon, Carlos Rozas, Hisham Shafi, Vedvyas Shanbhogue and Uday SavagaonkarIntel Corporation Abstract For years the PC community has struggled to provide secure solutions on open platforms. Intel has developed innovative new ...
      Intel® SHA Extensions Implementations
      By adminPosted 07/18/20130
      The Intel® Secure Hash Algorithm (SHA) Extensions are designed to improve the performance of SHA-1 and SHA-256 on Intel® Architecture (IA) processors. This code download provides optimized assembly and intrinsic routines using the Intel® SHA Extensions. A sample test application using published k...

      Pages

      Subscribe to
      No content found
      Subscribe to Intel Developer Zone Blogs
        Instruction set extensions programming reference, revision 18
        By Mark Charney (Intel)0
        In early February, an updated instruction set extensions programming reference, revision 18, has been posted here.  It includes information about: Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions Intel® Secure Hash Algorithm (Intel® SHA) extensions  Intel® Memory Protection Extensions (Intel® MPX)  For more information about the technologies: http://www.intel.com/software/isa
        Updated Intel® Software Development Emulator
        By Ady Tal (Intel)0
        Hello, we just released version 6.20 of the Intel® Software Development Emulator. It is available here:http://www.intel.com/software/sde It includes: Added support for XSAVEC and CLFLUSHOPT. Disabled TSX CPUID bits when TSX emulation is not requested. Improved disassembly for MPX instructions. Added an option for running chip-check only on the main executable. Added support for -quark (Pentium ISA). Added application debugging for Mac OSX with the lldb debugger.
        Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
        By Roman Dementiev (Intel)4
        Hi, you might find this collection of technical material about Intel TSX instructions useful: http://www.intel.com/software/tsx By a suggestion from some senior forum contributors I am making this post sticky. Best regards, Roman
        Links to instruction documentation
        By Thomas Willhalm (Intel)24
        The Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A and 2B (available here) are the instruction set reference. Haswell (2013) new instructionsare in theprogrammer's reference manual. In appendix C of the Intel 64 and IA-32 Architectures Optimization Reference Manual (available here), the latencies and throughput of instructions are listed. The documentation of the Intel C++ Compiler contains documentation of the intrinsics. The AVX Programming Reference and examples for using AVX are available on the AVX community page. (The interactive Intel Intrinsics Guide is also available there, which is useful for SSE programming as well.) The Intel Software Development Emulator (Intel SDE) allows simulation of future instructions.
        BUG: Poor hybrid SSE/AVX code generated
        By emmanuel.attia2
        Hi, I have a piece of code that I cannot disclose right now (I will try to reproduce it in a shorter example), the thing is when I compile it with /QAVX, it generate this code: Address Source Line Assembly Clockticks: Total Clockticks: Self Instructions Retired: Total Instructions Retired: Self CPI Rate: Total CPI Rate: Self General Retirement Microcode Sequencer Bad Speculation Back-end Bound Front-end Bound DTLB Overhead Loads Blocked by Store Forwarding Split Loads 4K Aliasing L2 Bound L3 Bound DRAM Bound Store Bound Core Bound ICache Misses ITLB Overhead Branch Resteers DSB Switches Length Changing Prefixes Front-End Bandwidth DSB Front-End Bandwidth MITE 0x100b931e 962 vmovdqu xmm5, xmmword ptr [ebx] 0.0% 4,983,341 0.0% 6,386,398 0.780 0.780 0.000 0.000 0.000 1.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0x100b9322 962 vmovdqu xmmword ptr [esp+0xa0], xmm5 1.8% 554,297,692 1.4% 698,936,006 0.793 0.793 0.130 0.000 0.00...
        Problem when using RTM
        By geomap0
        Hello, My name is George Mappouras and I am trying to make a simple program in order to evaluate the TSX in the new Haswell processors. However I came across a very strange problem that I can't find its cause and I was wondering if you could help me with it. The idea is simple, I have 'x' accounts and 'n' threads. Each thread does 'k' amount of transactions between random accounts (I transfer a random amount from account1 to account2 ). I tried this program with RTM, spinlocks and mutex (fine grained locking). In the end I check my results by comparing them to a single threaded version of this program. The problem is that in the case of the RTM (with or without fallback path) I noticed that sometimes the results don't match the single-threaded results.  I also noticed that this seems to happen only when I use hyperthreading. (The computer in which I test my program has 4 physical cores with hyperthreading, that means 8 threads max). I tried to debug my program and I suspect that the...
        asm blocks
        By berthou4
        Hello, I am writing AVX code inside asm blocks (don"t want to use avx intrinsics). A lot of gp registers are used and so they are mixed with the ones generated by the compiler and thus it is screwing the behavior of the code pretty fast. Is there an automatic or manual way to avoid these register overlaps ? Any link to documentation would be great. I would like also to use asm blocks in fortan with ifort, but didn't find the way yet. Thanks Vincent
        SDE produces unstable behavior
        By andysem2
        Hi, I have some SSE/AVX code that I'm trying to test with Intel Software Development Emulator (SDE) on CPUs without the native support for some of the instruction set extensions. In particular, I tried the following setups: 1. Sandy Bridge CPU, SDE is running with -hsw switch. 2. Sandy Bridge CPU, SDE is running with -hsw -sse-sde switches. 3. A KVM guest virtual machine with SSE4 instructions (host CPU is Nehalem), SDE is running with -hsw switch. All this is on Linux x86_64, SDE 6.22 and 6.12. What I'm seeing is when my code is running the emulated branch (i.e. AVX2 path or AVX path when AVX is emulated) I sometimes get corrupted results. The behavior is not stable, it can work correctly in one run and fail in the next one on the same input data. I'm sure my code is correct because I tried it on a Haswell machine and it works every time. Also, the AVX path is failing when emulated and not when executed natively. My code is single-threaded so there aren't any concurrency issues. I ...

        Pages

        Subscribe to Forums