Intel® Developer Zone:
Intel Instruction Set Architecture Extensions

Intel’s Instruction Set Architecture (ISA) continues to evolve to improve functionality, performance and the user experience. Featured below are planned extensions to the ISA that are new as well as those being planned for enhancements in future generations of processors. By publishing these extensions early, Intel helps ensure that the software ecosystem has time to innovate and come to market with enhanced and new products when the processors are launched.

Overview

Tools & Downloads

  • Intel® C++ Compiler

    The Intel® C++ Compiler is available for download from the Intel® Registration Center for all licensed customers. Evaluation versions of Intel® Software Development Products are also available for free download.

  • Intel Intrinsics Guide

    The Intel Intrinsics Guide is an interactive reference tool for Intel intrinsic instructions, which are C style functions that provide access to many Intel instructions – including Intel® Streaming SIMD Extensions (Intel® SSE), Intel® Advanced Vector Extensions (Intel® AVX), and more – without the need to write assembly code.

Intel® Advanced Vector Extensions (Intel® AVX)

The need for greater computing performance continues to grow across industry segments. To support rising demand and evolving usage models, we continue our history of innovation with the Intel® Advanced Vector Extensions (Intel® AVX) in products today.

Intel® AVX is a new-256 bit instruction set extension to Intel® SSE and is designed for applications that are Floating Point (FP) intensive. It was released early 2011 as part of the Intel® microarchitecture code name Sandy Bridge processor family and is present in platforms ranging from notebooks to servers. Intel AVX improves performance due to wider vectors, new extensible syntax, and rich functionality. This results in better management of data and general purpose applications like image, audio/video processing, scientific simulations, financial analytics and 3D modeling and analysis.

Intel® Advanced Vector Extensions 512 (Intel® AVX-512)

In the future, some new products will feature a significant leap to 512-bit SIMD support. Programs can pack eight double precision and sixteen single precision floating numbers within the 512-bit vectors, as well as eight 64-bit and sixteen 32-bit integers. This enables processing of twice the number of data elements that IntelAVX/AVX2 can process with a single instruction and four times the capabilities of Intel SSE.

Intel AVX-512 instructions are important because they open up higher performance capabilities for the most demanding computational tasks. Intel AVX-512 instructions offer the highest degree of compiler support by including an unprecedented level of richness in the design of the instruction capabilities.

Intel AVX-512 features include 32 vector registers each 512-bit wide and eight dedicated mask registers. Intel AVX-512 is a flexible instruction set that includes support for broadcast, embedded masking to enable predication, embedded floating point rounding control, embedded floating-point fault suppression, scatter instructions, high speed math instructions, and compact representation of large displacement values.

Intel AVX-512 offers a level of compatibility with Intel AVX which is stronger than prior transitions to new widths for SIMD operations. Unlike Intel SSE and Intel AVX which cannot be mixed without performance penalties, the mixing of Intel AVX and Intel AVX-512 instructions is supported without penalty. Intel AVX registers YMM0–YMM15 map into Intel AVX-512 registers ZMM0–ZMM15 (in x86-64 mode), very much like Intel SSE registers map into Intel AVX registers. Therefore, in processors with Intel AVX-512 support, Intel AVX and Intel AVX2 instructions operate on the lower 128 or 256 bits of the first 16 ZMM registers.

More information about the details about Intel AVX-512 instructions can be found in the blog "AVX-512 Instructions". The instructions are documented in the Intel® Architecture Instruction Set Extensions Programming Reference (see the "Overview" tab on this page).

An Embree-Based Viewport Plugin for Autodesk Maya* 2014 with Support for the Intel® Xeon Phi™ Coprocessor
By Charles Congdon (Intel)Posted 02/02/20150
Download PDF Purpose This code recipe describes how to obtain, build, and use the Embree-based Viewport Plugin for Autodesk Maya* 2014 on either Microsoft Windows* or Linux*. This plugin (actually a suite of plugins) runs under Autodesk Maya 2014 on the Intel® Xeon® processor (referred to as ‘h...
Quick Linking Intel® MKL BLAS, LAPACK to R
By Ying H (Intel)Posted 12/17/20140
Overview R is a popular programming language for statistical computing and machine learning. There is one article we published already- Using Intel® Math Kernel Library (Intel MKL) with R to show how to integrate Intel MKL BLAS and LAPACK libraries within R to improve the math computing performa...
Diagnostic 15542: Loop was not vectorized: inner loop was already vectorized.
By Devorah H. (Intel)Posted 10/30/20140
Product Version: Intel(R) Visual Fortran Compiler XE 15.0.0.070 Cause: The vectorization report generated when using Visual Fortran Compiler's optimization options ( -O2  -Qopt-report:2 ) states that loop was not vectorized since the inner loop was vectorized. Example: An example below will g...
Diagnostic 15541: Loop was not vectorized: outer loop was not auto-vectorized: consider using SIMD directive.
By Devorah H. (Intel)Posted 10/30/20140
Product Version: Intel(R) Visual Fortran Compiler XE 15.0.0.070 Cause: The vectorization report generated when using Visual Fortran Compiler's optimization options ( -O2 -assume:dummy_aliases -Qopt-report:2 ) states that loop was not vectorized due vector dependence, outer loop depends on inner...
Subscribe to Intel Developer Zone Articles
Vector programming. SSE4.2 to AVX2 conversion examples.
By Evgeny Stupachenko (Intel) Posted on 01/15/15 0
In this blog I’ll try to show how to convert SSE4.2 assembly to AVX2 (using the schemes from the blog Programming using AVX2) and how this affects performance. Easy case. When it is enough to add “v” prefix and replace “xmm” with “ymm”. Consider we have the following loop: for (i = 0; i < 10...
Additional AVX-512 instructions
By James Reinders (Intel) Posted on 07/17/14 1
Additional Intel® Advanced Vector Extensions 512 (Intel® AVX-512) The Intel® Architecture Instruction Set Extensions Programming Reference includes the definition of additional Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions. As I discussed in my first blog about Intel® AVX-...
Intel® Xeon™ E5-2600 v3 Product Family
By Khang Nguyen (Intel) Posted on 06/18/14 0
Based on Intel® Core™ microarchitecture (formerly codenamed Haswell) and manufactured on 22-nanometer process technology, these processors provide significant performance over the previous-generation Intel® Xeon™ processor E5-2600 v2 product family. This is the first Intel® Xeon® processor fami...
Optimizing Big Data processing with Haswell 256-bit Integer SIMD instructions
By gaston-hillar Posted on 06/11/14 0
Big Data requires processing huge amounts of data. Intel Advanced Vector Extensions 2 (aka AVX2) promoted most Intel AVX 128-bits integer SIMD instruction sets to 256-bits. Intel AVX brought 256-bits floating-point SIMD instructions, but it didn't include 256-bits integer SIMD instructions. Intel...
Subscribe to Intel Developer Zone Blogs

    Intel® Software Guard Extensions (Intel® SGX)

    Intel Vision Statement

    Computing workloads today are increasing in complexity, with hundreds of software modules delivered by different teams scattered across the world. Isolation of workloads on open platforms has been an ongoing effort, beginning with protected mode architecture to create a privilege separation between operating systems and applications. Recent malware attacks however have demonstrated the ability to penetrate into highly privileged modes and gain control over all the software on a platform.

    Intel® Software Guard Extensions (Intel® SGX) is a name for Intel Architecture extensions designed to increase the security of software through an “inverse sandbox” mechanism. In this approach, rather than attempting to identify and isolate all the malware on the platform, legitimate software can be sealed inside an enclave and protected from attack by the malware, irrespective of the privilege level of the latter. This would complement the ongoing efforts in securing the platform from malware intrusion, similar to how we install safes in our homes to protect valuables even while introducing more sophisticated locking and alarm systems to prevent and catch intruders.

    Getting Started (common to all ISA)

    Overview

    Tools & Downloads

    • No change to existing content

    Technical Content

    Intel® SGX for Dummies – Part 3
    By Matthew Hoekstra (Intel) Posted on 09/01/14 3
    In my previous two blog posts I provided an overview of the Intel® SGX design objectives.  Without further ado, below is a more detailed description of the remaining design objectives. As a reminder, I highlighted these eight design objectives for Intel® SGX: Allow application developers to pro...
    Intel® SGX for Dummies – Part 2
    By Matthew Hoekstra (Intel) Posted on 06/02/14 0
    In my last blog post, only about 9 short months ago, I provided an overview of the Intel® SGX design objectives.  Sincere apologies for the long delay between postings, my colleagues and I have been hard at work on the latest security technologies and I need to remember to carve out more time to ...
    Intel® SGX for Dummies (Intel® SGX Design Objectives)
    By Matthew Hoekstra (Intel) Posted on 09/26/13 4
    Today the Intel® Software Guard Extensions (Intel® SGX) programming reference manual was published (more information is available here).  Given the significant time and effort that my colleagues and I have spent defining Intel® SGX, I can't find a strong enough word in my thesaurus to describe ho...
    Attestation & Sealing with Software Guard Extensions
    By Simon Johnson (Intel) Posted on 09/18/13 1
    Once you have instantiated a secured software environment (known as an enclave) with the new instructions from the Intel(r) Software Guard Extensions (SGX) you are now ready to load secrets into it for processing and storing on the platform. This is the purpose of the attestation and sealing feat...
    Subscribe to Intel Developer Zone Blogs
    How to use XDB to do kernel debug on Yocto with Minnowboard MAX
    By ALICE H. (Intel)Posted 01/12/20151
    Introduction Minnowboard MAX is an open hardware which is utilized Intel Atom processor. This hardware is a small and low cost but offer exceptional performance, flexibility, openness and standards. We can prepare micro sd card or usb flash device to expand the hardware storage and easy exchange...
    Innovative Technology for CPU Based Attestation and Sealing
    By adminPosted 08/14/20130
    Download white paper as PDF By:Ittai Anati, Shay Gueron, Simon P Johnson, Vincent R Scarlata Intel Corporation Abstract Intel is developing the Intel® Software Guard Extensions (Intel® SGX) technology, an extension to Intel® Architecture for generating protected software containers. The container...
    Using Innovative Instructions to Create Trustworthy Software Solutions
    By adminPosted 08/14/20130
    Download white paper as PDF By:Matthew Hoekstra, Reshma Lal, Pradeep Pappachan, Carlos Rozas, Vinay Phegade, Juan del Cuvillo Intel Corporation Abstract Software developers face a number of challenges when creating applications that attempt to keep important data confidential. Even diligent use o...
    Innovative Instructions and Software Model for Isolated Execution
    By adminPosted 08/14/20130
    Download white paper as PDF By:Frank McKeen, Ilya Alexandrovich, Alex Berenzon, Carlos Rozas, Hisham Shafi, Vedvyas Shanbhogue and Uday SavagaonkarIntel Corporation Abstract For years the PC community has struggled to provide secure solutions on open platforms. Intel has developed innovative new ...
    Subscribe to Intel Developer Zone Articles

    Intel® Memory Protection Extensions (Intel® MPX)

    Computer systems face malicious attacks of increasing sophistication, and one of the more commonly observed forms is to cause or exploit buffer overruns (or overflows) in software applications.

    Intel® Memory Protection Extensions (Intel® MPX) is a name for Intel Architecture extensions designed to increase robustness of software. Intel MPX will provide hardware features that can be used in conjunction with compiler changes to check that memory references intended at compile time do not become unsafe at runtime. Two of the most important goals of Intel MPX are to provide this capability at low overhead for newly compiled code, and to provide compatibility mechanisms with legacy software components. Intel MPX will be available in a future Intel® processor.

    Pointer Checker in ICC: requires dynamic linking of runtime libraries
    By Kittur Ganesh (Intel)Posted 07/10/20140
    The -check-pointers switch, which enables the Pointer Checker feature, cannot be used with the -static flag on Linux* (/MT on Windows*) which forces all Intel libraries to be linked statically. The reason is that, by design, the Pointer Checker library “libchkp.so” must be shared by all executabl...
    Using Intel® SDE's chip-check feature
    By Mark Charney (Intel)Posted 10/03/20130
    Intel® SDE includes a software validation mechanism to restrict executed instructions to a particular microprocessor. This is intended to be a helpful diagnostic tool for use when deploying new software. Use chip check when you want to make sure that your program is not using instruction features...
    Using Intel® MPX with the Intel® Software Development Emulator
    By Ady Tal (Intel)Posted 07/23/20131
    Intel has announced a new technology called Intel® Memory Protection Extensions (Intel® MPX). To find out more, check out the Instruction Set Extensions web pages.  Once you know about Intel MPX, you may want to experiment with Intel® SDE. This article explains how to run Intel MPX with Intel SDE...
    Linux* ABI
    By Milind Girkar (Intel)Posted 07/18/20130
    by Milind Girkar, Hongjiu Lu, David Kreitzer, and Vyacheslav Zakharin (Intel) Description of the Intel® AVX, Intel® AVX2, Intel® AVX-512 and Intel® MPX extensions required for the Intel® 64 architecture application binary interface.
    Subscribe to Intel Developer Zone Articles
    Intel® Memory Protection Extensions (Intel® MPX) Runtime Support
    By Brian Vajda (Intel) Posted on 07/23/13 0
    Enabling an application to use Intel MPX will generally not require source code updates but there is some runtime code needed in order to make use of Intel MPX.  For most applications this runtime support will be available by linking to a library supplied by the compiler or possibly it will come ...
    Intel® Memory Protection Extensions (Intel® MPX) Design Considerations
    By Baiju Patel. (Intel) Posted on 07/23/13 0
    My very first exposure to buffer overflow was with Morris worm in 80’s and since then, we collectively have tried to get a good handle on buffer overflow as it impacts both security and robustness of C/C++ software. Needless to say, we have made significant progress with addressing buffer overfl...
    Intel® Memory Protection Extensions (Intel® MPX) support in the GNU toolchain
    By Igor Zamyatin (Intel) Posted on 07/22/13 0
    Invalid memory access problem is commonly found in many C/C++ programs and leads to time consuming debugging, program instability and vulnerability. Many attacks exploit software bugs related to inappropriate memory accesses caused by buffer overflow (or buffer overruns). Existing set of techniq...
    Subscribe to Intel Developer Zone Blogs

      Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)

      The Secure Hash Algorithm (SHA) is one of the most commonly employed cryptographic algorithms.  Primary usages of SHA include data integrity, message authentication, digital signatures, and data de-duplication.  As the pervasive use of security solutions continues to grow, SHA can be seen in more applications now than ever. The Intel® SHA Extensions are designed to improve the performance of these compute intensive algorithms on Intel® architecture-based processors.

      The Intel® SHA Extensions are a family of seven Intel® Streaming SIMD Extensions (Intel® SSE)-based instructions that are used together to accelerate the performance of processing SHA-1 and SHA-256 on Intel architecture-based processors.  Given the growing importance of SHA in our everyday computing devices, the new instructions are designed to provide a needed boost of performance to hashing a single buffer of data. The performance benefits will not only help improve responsiveness and lower power consumption for a given application, they may enable developers to adopt SHA in new applications to protect data while delivering to their user experience goals. The instructions are defined in a way that simplifies their mapping into the algorithm processing flow of most software libraries, thus enabling easier development.

      Innovative Technology for CPU Based Attestation and Sealing
      By adminPosted 08/14/20130
      Download white paper as PDF By:Ittai Anati, Shay Gueron, Simon P Johnson, Vincent R Scarlata Intel Corporation Abstract Intel is developing the Intel® Software Guard Extensions (Intel® SGX) technology, an extension to Intel® Architecture for generating protected software containers. The container...
      Using Innovative Instructions to Create Trustworthy Software Solutions
      By adminPosted 08/14/20130
      Download white paper as PDF By:Matthew Hoekstra, Reshma Lal, Pradeep Pappachan, Carlos Rozas, Vinay Phegade, Juan del Cuvillo Intel Corporation Abstract Software developers face a number of challenges when creating applications that attempt to keep important data confidential. Even diligent use o...
      Innovative Instructions and Software Model for Isolated Execution
      By adminPosted 08/14/20130
      Download white paper as PDF By:Frank McKeen, Ilya Alexandrovich, Alex Berenzon, Carlos Rozas, Hisham Shafi, Vedvyas Shanbhogue and Uday SavagaonkarIntel Corporation Abstract For years the PC community has struggled to provide secure solutions on open platforms. Intel has developed innovative new ...
      Intel® SHA Extensions Implementations
      By adminPosted 07/18/20130
      The Intel® Secure Hash Algorithm (SHA) Extensions are designed to improve the performance of SHA-1 and SHA-256 on Intel® Architecture (IA) processors. This code download provides optimized assembly and intrinsic routines using the Intel® SHA Extensions. A sample test application using published k...
      Subscribe to Intel Developer Zone Articles
      Intel® Xeon™ E5-2600 v3 Product Family
      By Khang Nguyen (Intel) Posted on 06/18/14 0
      Based on Intel® Core™ microarchitecture (formerly codenamed Haswell) and manufactured on 22-nanometer process technology, these processors provide significant performance over the previous-generation Intel® Xeon™ processor E5-2600 v2 product family. This is the first Intel® Xeon® processor fami...
      Subscribe to Intel Developer Zone Blogs
        Updated Intel® Software Development Emulator
        By Mark Charney (Intel)7
        Hello, On October 2, 2014, we released version 7.8 of the Intel® Software Development Emulator. It is available here: http://www.intel.com/software/sde   See the release notes for a full list of changes.   This release includes:   Support for AVX512 VBMI and AVX512 IFMA instructions Better support for running on Haswell hosts Updated CPUID information For more information on the new instructions see http://www.intel.com/software/isa  
        Resources about Intel® Transactional Synchronization Extensions (Intel TSX)
        By Roman Dementiev (Intel)4
        Hi, you might find this collection of technical material about Intel TSX instructions useful: http://www.intel.com/software/tsx By a suggestion from some senior forum contributors I am making this post sticky. Best regards, Roman
        Links to instruction documentation
        By Thomas Willhalm (Intel)25
        Intel Instruction Set Architecture Extensions  Intel® Architecture Instruction Set Extensions Programming Reference includes: Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions (AVX512F, AVX512DQ, AVX512BW, AVX512VL, AVX512CD, AVX512PF, AVX512ER) Intel® Secure Hash Algorithm (Intel® SHA) extensions Intel® Memory Protection Extensions (Intel® MPX) The Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A and 2B (available here) are the instruction set reference. Haswell (2013) new instructionsare in theprogrammer's reference manual. In appendix C of the Intel 64 and IA-32 Architectures Optimization Reference Manual (available here), the latencies and throughput of instructions are listed. The documentation of the Intel C++ Compiler contains documentation of the intrinsics. The AVX Programming Reference and examples for using AVX are available on the AVX community page. (The interactive Intel Intrinsics Guide is also available there, which is usef...
        How to work with AVX on windows
        By siva rama k.4
        Hi, I am interested in AVX instructions set using in my application for speed up.But i am new to AVX. How can i know whether my system processor is able to support AVX or not? My System Configurations as OS; Windows 7 with 64-bit CPU: Inter(R) Xeon(R) CPU  W3505 @2.53GHz. Anybody can help me.. Thanks in Advance.  
        Is profiling information running on SDE accurate and trustable?
        By WEI Z. (Intel)1
        Hi,          I am trying to look at AVX 512 performance, currently, I wrote a simple function for evaluation as below, I configured the optimization and enabled AVX-512 etc in the project properties setting(vs2013 integrated with Intel-parallel-studio ), and I see the AVX-512 instructions are used from the asm files generated by compiler. void complexVectorConjMpy(float *inputPtr1, float *inputPtr2, float *outputPtr, int numData) {     int idxData;     float data1Re, data1Im, data2Re, data2Im;     #pragma ivdep     __assume_aligned(inputPtr1, 64);     __assume_aligned(inputPtr2, 64);     __assume_aligned(outputPtr, 64);           for (idxData = 0; idxData < numData; idxData++)     {         data1Re = inputPtr1[2 * idxData];         data1Im = inputPtr1[2 * idxData + 1];         data2Re = inputPtr2[2 * idxData];         data2Im = inputPtr2[2 * idxData + 1];                  outputPtr[2 * idxData]     = data1Re * data2Re + data1Im * data2Im;         outputPtr[2 * idx...
        TSX example code doesn't work
        By YangHun P.5
        I have intel xeon cpu E3-1230 v3 machine which has TSX. I just want to test that TSX runs well. From manual, i got this example pseucode void rtm_wrapped_lock(lock) { if (_xbegin() == _XBEGIN_STARTED) { if (lock is free) /* add lock to the read-set */ return; /* Execute transactionally */ _xabort(0xff); /* 0xff means the lock was not free */ } /* come here following the transactional abort */ original_locking_code(lock); } void rtm_wrapped_unlock(lock) { /* If lock is free, assume that the lock was elided */ if (lock is free) _xend(); /* commit */ else original_unlocking_code(lock); }My test code for RTM which is a set of TSX is like this. void main(void) { int i; int sum[20]; int data[20]; pthread_mutex_t mutex; pthread_mutex_init(&mutex,NULL); for(i=0;i<20;i++) { data[i]=i; sum[i]=0; } omp_set_num_threads(4); #pragma omp parallel for private(i) for(i=0;i<2...
        SDE 7.15 for Linux has no 64-bit libs
        By andysem3
        The recently released SDE 7.15 for Linux seem to have 32-bit libraries instead of 64-bit in intel64/pin_ext_lib and intel64/xed_ext_lib. Is this an oversight or am I missing something?  
        SSE ucomiss/comiss strange behavior
        By Naer J.7
        Hello. When I run this code : #include <cmath> // for NAN c++11 and up #include <iostream> #include <xmmintrin.h> int main(int argc, char ** argv) { float nan_value = NAN; __m128 const a = _mm_load_ss(&nan_value); __m128 const b = _mm_setzero_ps(); std::cout << "gt : " << (nan_value > 0) << std::endl; std::cout << "lt : " << (nan_value < 0) << std::endl; std::cout << "ge : " << (nan_value >= 0) << std::endl; std::cout << "le : " << (nan_value <= 0) << std::endl; std::cout << "eq : " << (nan_value == 0) << std::endl; std::cout << "ne : " << (nan_value != 0) << std::endl << std::endl << std::endl; std::cout << "ugt : " << _mm_ucomigt_ss(a,b) << std::endl; std::cout << "ult : " << _mm_ucomilt_ss(a,b) << std::endl; std::cout << "uge : " << _mm_ucomige_ss(a,b) << ...
        Subscribe to Forums