Software debugging over the Joint Test Action Group (JTAG) has some fundamental requirements:
- A reliable target connection
- A JTAG-enabled CPU
- Knowledge of the implementation of the platform being debugged
Reliable target connection
With a reliable target connection, the signaling requirements of JTAG are met, and communication at the JTAG protocol level is possible. Additionally, there may be sideband signals that are not part of the generic JTAG spec, but are required for debugging Intel® processors. Specific requirements for each platform are described in the "Debug Port Design Guide" available from Intel.
Some Intel processors are not factory-enabled for JTAG debugging, while others may limit JTAG-accessible functions depending on fusing, firmware configuration, board strappings, or other factors. Note that "enabled" refers to the processor core, which is required for software debugging. Even if the processor is disabled, it is still possible for the fundamental JTAG connection to work, and access to other SoC resources to be possible.
The last 10% of the solution requires platform-specific knowledge to keep the debugger out of trouble. Examples include knowledge of watchdog timers, memory or flash layout, PCI topology, or other platform implementation-specific details that can inhibit or disrupt the debug session.