Discover the Terasic DE10-Nano Kit

Based on a Cyclone® V SoC FPGA, this kit provides a reconfigurable hardware design platform for makers, educators, and IoT system developers. The board contained in the kit features two general purpose input/output (GPIO) expansion headers and an Arduino* header so you can connect to a wide range of sensors.

Get Started   Buy

Follow the Global Competition

Project development begins in the Terasic Innovate FPGA Design Contest. Track each team's progress as they post design papers and videos.

Learn More


Example Designs

Inside the Kit

This kit includes a variety of reference designs, tools, and documentation designed for different types of developers.

  • For embedded software developers, the system-on-chip (SoC) boots to the Linux* operating system, runs web and virtual network computing (VNC) servers, and provides reference designs, development tools, and tutorials to accelerate the learning curve of developing software.
  • For hardware developers, the SoC provides reference designs and tutorials to guide you through your first field-programmable gate array (FPGA), hard processor system (HPS), and system designs.
  1. DE10-Nano board
  2. DE10-Nano quick start guide
  3. USB Type A to Mini-B cable
  4. USB Type A to Micro-B cable
  5. DC power adapter (5 V)
  6. microSD* card (installed)


Hard Processor System


Dual-core ARM* Cortex*-A9 MPCore processor at 800 MHz

neon™ media-processing engine with double-precision floating point unit (FPU)

32 KB L1 instruction cache

32 KB L1 data cache

512 KB shared L2 cache



64 KB on-chip SRAM

1 GB DDR3 SDRAM (32-bit data)

8 GB microSD* flash memory card

Processor I/O

1 gigabit Ethernet PHY with RJ45 connector

1 USB 2.0 On-The-Go (OTG) port, USB Micro-AB connector

microSD* card interface and socket

Accelerometer (I2C interface plus interrupt)

UART to USB, USB Mini-B connector

Warm reset button, cold reset button

One user button and one user LED

Expansion header for use with Linear Technology* DC934A dual 16-bit digital-to-analog converter daughter card

Embedded Software

Linux* kernel 4.1.33 LTSI

Angstrom 2016.12


Programmable Logic

Logic elements (LE): 110 K LE

5,570 kilobits memory

224 18 x 19 multipliers

112 variable precision DSP blocks

6 phased-locked loops (PLL)

145 user-defined I/O


FPGA Configuration Sources

Embedded USB-Blaster* II (JTAG) cable

Serial configuration flash - EPCS128

ARM* Cortex*-A9 hard processor system (HPS)

FPGA I/O Interfaces

2 push buttons

4 slide switches

8 LEDs

Three 50 MHz clock sources from the clock generator

Two 40-pin expansion headers with diode protection

One Arduino* expansion header (Arduino UNO* R3 compatibility), can connect with Arduino shields

One 10-pin analog input expansion header (shared with Arduino analog input)

8-channel, 12-bit A/D converter, 500 ksps, 4-pin serial peripheral interface (SPI)

FPGA Hardware Design

32-bit fast Fourier transform (FFT) engine

HDMI* output (video pipeline)

GPIO for LEDs, push buttons, and slide switches

I/F to Arduino shield headers (digital I/O, serial I/O, A/D converter)