Discover the Terasic DE10-Nano Kit

Based on a Cyclone® V SoC FPGA, this kit provides a reconfigurable hardware design platform for makers, educators, and IoT system developers.

  • Equipped with high-speed DDR3 memory
  • Includes 2 GPIO expansion headers
  • Analog-to-digital capabilities

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Optimized to Boost Performance

Maximize performance, offload traditional CPU processing, and tailor the compute power to specific applications.

I/O Expansion Support

Enhance your design with the hardware support to expand I/O and create a custom peripheral set.

Flexible and Adaptive

Run state-of-the-art applications with the flexibility to adapt to evolving standards, algorithms, and threats.

Kit Details


  • DE10-Nano board
  • DE10-Nano quick start guide
  • USB Type A to Mini-B cable
  • USB Type A to Micro-B cable
  • DC power adapter (5 V)
  • microSD* card (installed)

Preinstalled Software

  • System-on-chip (SoC) boots to the Linux* operating system
  • Web and virtual network computing (VNC) servers
  • Reference designs
  • Development tools


Hard Processor System


Dual-core ARM Cortex*-A9 MPCore processor at 800 MHz
neon™ framework media-processing engine with double-precision floating point unit (FPU)
32 KB L1 instruction cache
32 KB L1 data cache
512 KB shared L2 cache


64 KB on-chip SRAM
1 GB DDR3 SDRAM (32-bit data)
8 GB microSD* flash memory card

Processor I/O

1 gigabit Ethernet PHY with RJ45 connector
1 USB 2.0 On-The-Go (OTG) port, USB Micro-AB connector
microSD* card interface and socket
Accelerometer (I2C interface plus interrupt)
UART to USB, USB Mini-B connector
Warm reset button, cold reset button
One user button and one user LED
Expansion header for use with Linear Technology* DC934A dual 16-bit digital-to-analog converter daughter card

Embedded Software

Linux* kernel 4.1.33 LTSI
Angstrom 2016.12


Programmable Logic

Logic elements (LE): 110 K LE
5,570 kilobits memory
224 18 x 19 multipliers
112 variable precision DSP blocks
6 phased-locked loops (PLL)
145 user-defined I/O

Configuration Sources

Embedded USB-Blaster* II (JTAG) cable
Serial configuration flash - EPCS128
ARM Cortex*-A9 hard processor system (HPS)

I/O Interfaces

2 push buttons
4 slide switches
8 LEDs
3 clock sources (50 MHz) from the clock generator
2 expansion headers (40-pin) with diode protection
1 Arduino* expansion header compatible with Arduino UNO* R3 (can connect with Arduino shields)
1 analog input expansion header (10-pin) shared with Arduino analog input
8-channel, 12-bit A/D converter, 500 ksps, 4-pin serial peripheral interface (SPI)

Hardware Design

32-bit fast Fourier transform (FFT) engine
HDMI* output (video pipeline)
GPIO for LEDs, push buttons, and slide switches
I/F to Arduino shield headers (digital I/O, serial I/O, A/D converter)

Compatible Accessory Boards

Digital Camera Kit (8 MP)

Wireless Connectivity Board

Servo Motor Kit

Multitouch LCD Module

LCD Touch Module (2.4 in.)

Documentation & Downloads


Embedded Software Development Tools

Download and install the Intel® SoC FPGA Embedded Development Suite (SoC EDS). Applications are written in the C programming language.


FPGA Design Software

Intel® Quartus® Prime Design Software (specifically the "Lite" version of the software) is used for FPGA hardware development. Programs are written in a hardware description language, such as Verilog or VHDL.


Software Utilities

Recommended development software includes the following:

  • PuTTY
  • Download this remote access software to the host system (such as your laptop) to control the board from the host system: VNC Viewer*
  • Select your SD card imager based your operating system:
  • Share your PC keyboard and mouse with the Terasic DE10-Nano board for development: Synergy Software
  • Get virtual COM port drivers that enable UART over USB: FTDI

microSD* Card Images

Get the software source files to create the card image, as well as release notes.


Source Files

Access source files and scripts for generating the hardware and software design from these Git* repositories.

FPGA Project Files

  • Master branch: Contains the FPGA source files used to create the hardware design
  • Release builds: Contains the latest compiled version of the project


Obtain the recipes to generate the board support package (BSP)

Web Content

Contains the HTML, scripts, documents (PDF documents such as the user manual) and graphics used to build the web pages served by the board.


Contains Windows* setup information file (INF) for the installation of the Remote Network Driver Interface Specification (RNDIS) driver, which enables Ethernet over USB.