As the world of high-performance computing (HPC) evolves and becomes accessible, use this starting point to optimization and gaining better compute performance. While many applications already use features of modern hardware, many more do not extract parallelism in their algorithms, nor do they leverage other new capabilities including larger caches, Single Instruction Multiple Data (SIMD), threading, fabric technology, new file architecture, and nonvolatile memory technology.
Invited Talk Series
Presented by global partners who use Intel® architecture for scientific breakthroughs, these talks share optimization techniques, best practices, and results. This series is for students, educators, developers, scientists, data analysts, system administrators, and more, who work to maximize software efficiency using Intel® technology.
Scale Data-Intensive & Deep Learning Applications
Taylor Childers is a computational scientist at the Argonne Leadership Computing Facility (ALCF), which is helping to shape the new landscape of scientific computing.
Working with researchers in various domains, ALCF scientists are optimizing popular machine learning frameworks (such as TensorFlow* and PyTorch*) to understand scaling performance and reduce the time to a solution. This presentation describes this research program and tools that support the program.
May 30, 2019
8:00 a.m. – 8:30 a.m. Pacific standard time
A Lightweight Library for Flexible In-Transit Visualization
Will Usher is part of the Scientific Computing and Imaging Institute at the University of Utah
As simulations grow in scale, so does the need for in situ analysis methods, such as in-transit visualization, to handle the large amount of data produced. Get a demonstration on batch analysis and interactive visualization using libIS.
July 25, 2019
8:00 a.m. – 8:30 a.m. Pacific standard time
This collection of self-paced training and reference materials provides an overview of parallel programming on Intel® architecture.
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Intel® Xeon® Processors & Intel® Xeon Phi™ Product Family
Learn how to modernize code for the Intel® Xeon Phi™ processors. Gain insight for OpenMP*, Intel® MPI Library, and Intel® software to write code using better vectorization and parallelism for hardware optimization.
Why Use Code Modernization?
The Purpose of Intel® Many Integrated Core Architecture
Think Parallel: Modern Applications for Modern Hardware
Parallel Programming Models and Optimization Strategies
Deep Dive with Code Modernization Experts
Solutions for Lustre* Training
Use these materials to further your knowledge of the Lustre* file system, gain deeper insight into solutions from Intel, and explore fundamental concepts and advanced implementation and configuration details.
Intel® Omni-Path Architecture (Intel® OPA) Training
The next generation of HPC switch technology, Intel® Omni-Path Fabric (Intel® OP Fabric), is designed for improving system-level packaging and network efficiency. It enables a broad class of computations requiring scalable, tightly coupled processor, memory, and storage resources. These training materials help you become familiar with Intel® OPA.
Next-Generation Fabric: Details on the Intel OPA
Advanced Features of the Intel OPA Network Layers
Democratize Best-in-Class Interconnect Performance
The Intel OPA Launch
Maximize HPC Storage Performance
Intermediate & Advanced
Access hands-on workshops, code samples, case studies, and domain-focused training to get the most out of your code on Intel architecture. We also encourage you to check out the Intel® Software Innovator and Intel® Black Belt Software Developer Program.
Intel Xeon Processors & Intel Xeon Phi Product Family
Get continued training for OpenMP*, Intel MPI Library, Intel® Parallel Studio, Intel Xeon Phi processor and coprocessor, expressing parallelism, and performance optimization methods.
Multi-Channel DRAM (MCDRAM) on Intel Xeon Phi Products – Analysis Methods and Tools
How to Detect Intel AVX-512 Support (Intel Xeon Phi Processor)
Scale your Application Across Shared and Distributed Memory
Squashing Races, Deadlocks, and Memory Bugs
Software Defined Visualization: Data Analysis for Current and Future Cyber Infrastructure
Benefits of Leveraging Software Defined Visualization (OSPRay)
From Correct to Correct and Efficient with Molecular Dynamics Benchmarks
From Correct to Correct and Efficient with Hydro2D
Optimization of Vector Arithmetics in Intel Architecture
Optimization of Multithreading in Intel Architecture
Gain Performance through Vectorization Using Fortran
Exploit Multilevel Parallelism in HPC Applications
Roofline Analysis: Visualize Impact of Compute Versus Memory Optimizations
Solutions for Lustre Training
This advanced training is for anyone who wishes to further their knowledge of the file system and gain deeper insights into solutions from Intel for software. The training exposes you to many implementation concepts and configuration details.