BLAS Level 3 Routines
BLAS Level 3 routines perform matrixmatrix operations. Table “BLAS Level 3 Routine Groups and Their Data Types” lists the BLAS Level 3 routine groups and the data types associated with them.
Routine Group 
Data Types 
Description 

s, d, c, z 
Computes a matrixmatrix product with general matrices. 

c, z 
Computes a matrixmatrix product where one input matrix is Hermitian. 

c, z 
Performs a Hermitian rankk update. 

c, z 
Performs a Hermitian rank2k update. 

s, d, c, z 
Computes a matrixmatrix product where one input matrix is symmetric. 

s, d, c, z 
Performs a symmetric rankk update. 

s, d, c, z 
Performs a symmetric rank2k update. 

s, d, c, z 
Computes a matrixmatrix product where one input matrix is triangular. 

s, d, c, z 
Solves a triangular matrix equation. 
Symmetric Multiprocessing Version of Intel® MKL
Many applications spend considerable time executing BLAS routines. This time can be scaled by the number of processors available on the system through using the symmetric multiprocessing (SMP) feature built into the Intel MKL Library. The performance enhancements based on the parallel use of the processors are available without any programming effort on your part.
To enhance performance, the library uses the following methods:

The BLAS functions are blocked where possible to restructure the code in a way that increases the localization of data reference, enhances cache memory use, and reduces the dependency on the memory bus.

The code is distributed across the processors to maximize parallelism.
Optimization Notice 

Intel's compilers may or may not optimize to the same degree for nonIntel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessordependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 