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Best Practices and Performance Studies for High-Performance Computing Clusters

Best Practices and Performance Studies for High-Performance Computing Clusters

Last updated: October 27, 2017Video length: 56 min

Maximize application performance in high-performance computing (HPC) workloads using key tunable elements.

The State of High-Performance Computing in the Open-Source R Ecosystem

Last updated: October 27, 2017Video length: 48 min

A history and current use of the R language on high-performance computing (HPC) resources.

Realizing Multi-Hit Ray Tracing in Embree and OSPRay

Realizing Multi-Hit Ray Tracing in Embree and OSPRay

Last updated: October 26, 2017Video length: 54 min

This session discusses multi-hit ray traversal—a class of ray traversal algorithms that finds one or more primitives intersected by a ray and ordered by point of intersection.

Accelerate Big Data Processing with High-Performance Computing Technologies

Accelerate Big Data Processing with High-Performance Computing Technologies

Last updated: October 26, 2017Video length: 52 min

Learn about opportunities and challenges for accelerating big data middleware on modern high-performance computing (HPC) clusters by exploiting HPC technologies.

Massively Parallel K-Nearest Neighbor Computation on Distributed Architectures

Last updated: October 26, 2017Video length: 49 min

This session discuss the implementation and performance of the K-nearest neighbor (KNN) computation on a distributed architecture using the Intel® Xeon Phi™ processor

SDVIs and In-Situ Visualization on TACC's Stampede

SDVis and In-Situ Visualization on Texas Advanced Computing Center's (TACC) Stampede

Last updated: October 26, 2017Video length: 1 hr 19 min

This talk presents recent work in high-fidelity visualization using the OSPRay ray tracing framework on the Texas Advanced Computing Center's (TACC) local and remote visualization systems.

Data Analytics, Machine Learning, and High-Performance Computing in Today’s Changing Application Environment

Last updated: October 25, 2017Video length: 51 min

This session describes what solutions companies want, how these companies may differ from the more “classical” consumers of machine learning and analytics, and the rising challenges that current and future high-performance computing (HPC) development may have to cope with.

Accelerate Machine Learning Software on Intel® Architecture

Last updated: October 25, 2017Video length: 28 min

This session presents performance data for deep learning training for image recognition that achieves greater than 24 times speedup performance with a single Intel® Xeon Phi™ processor 7250 when compared to Caffe*. In addition, we present performance data that shows training time is further reduced by 40 times the speedup with a 128-node Intel® Xeon Phi™ processor cluster over Intel® Omni-Path Architecture (Intel® OPA).

Performance Optimization of Deep Learning Frameworks Caffe* and TensorFlow* for the Intel® Xeon Phi™ Product Family

Last updated: October 25, 2017Video length: 52 min

In this talk, we analyze the performance characteristics of Caffe* and TensorFlow* on an Intel® Xeon Phi™ processor x200.

The Modern Code Developer Challenge

As part of its ongoing support of the world-wide student developer community and advancement of science, Intel has partnered with CERN through CERN openlab to sponsor the Intel® Modern Code Developer Challenge. The goal for Intel is to give budding developers the opportunity to use modern...

Michelle Chuaprasert

Students at the Intel® HPC Developer Conference

Join Michelle Chuaprasert at “Meet the Experts” on Saturday 5:30-7:30 p.m. at the Intel® HPC Developer Conference. We’ll talk about our on-going support of the student developer community with conferences such as this as well as programs, learning and networking opportunities and more.

Intel® Parallel Computing Center at Computer Network Information Center of Chinese Academy of Sciences

Published on April 7, 2015, updated October 20, 2017

Principal Investigators: Xuebin Chi is currently Professor in the Computing Scientific Application Center, Computer Network Information Center, Chinese Academy of Sciences. Dr. Chi is Director of Supercomputing Center & Vice Director of CNIC. His research focuses on Computational...

Intel® Parallel Computing Center at CINECA

Principal Investigator: Dr. Sanzio Bassini, Dr. PhD Carlo Cavazzoni CINECA is a nonprofit Consortium, made up of Italian universities and Institutions - it hosts one of the largest public Italian computing centres, with EMEA and worldwide visibility and influence. CINECA has high expertise in...

Deep Learning Training and Testing on a Single Node Intel® Xeon® Scalable Processor System Using Intel® Optimized Caffe*

I. Introduction This document provides step-by-step instructions on how to train and test your trained single node Intel® Xeon® Scalable processor platform system, using an Intel® distribution of Caffe* framework for image recognition datasets (CIFAR10, MNIST). This document provides beginner...

Intel® Parallel Computing Center at Argonne Leadership Computing Facility - Argonne National Laboratory

Published on February 23, 2016, updated October 20, 2017

Principal Investigators: Anouar Benali obtained a Ph.D. in Theoretical Physical Chemistry from the University of Toulouse (France) in 2010. He is an Assistant Computational Scientist at the Argonne Leadership Computing Facility and a fellow of the Computation Institute at the University of...

Fujitsu Offers Remote Access to HPC Clusters

Last updated: October 19, 2017Video length: 2 min

The Fujitsu Remote Access Program* offers an opportunity to run HPC workloads on a high-performance cluster

Rescale SCALEX* Offers SAAS Platform for HPC-Applications

Last updated: October 19, 2017Video length: 2 min

Rescale ScaleX* is an innovative web-based environment enabling HPC applications to run on the latest Intel technology.

DKRZ German Weather Forecasting Service Visualization Demo

Last updated: October 17, 2017Video length: 2 min

Software on Intel® Xeon® processors doing high quality rendering for visual data representation.

Intel® Xeon Phi™ Processor Applications

This presentation is an expanding collection of Intel® Xeon Phi™ processor application showcase and proof points that demonstrate improved software performance for key applications and benchmarks in key business segments, such as Manufacturing, Life Sciences, Finance, Energy and more.

Best of Modern Code October

The Best of Modern Code | October

Don't miss your chance--Register now for the Intel® HPC Developer Conference happening next month. This month you can read about cells in the cloud, future-proofing your code and mode collapse in GANS.

October Top Ten

Top Ten Intel Software Developer Stories | October

Learn to build a face access control solution, get horrified in a haunted high school, and be sure to register for the Intel® HPC Developer Conference this month.

Improve Performance Using Vectorization and Intel® Xeon® Scalable Processors

Introduction Modern CPUs include different levels of parallelism. High-performance software needs to take advantage of all opportunities for parallelism in order to fully benefit from modern hardware. These opportunities include vectorization, multithreading, memory optimization, and more. The...

Writing own-vector algorithms in OpenJDK* for faster performance

In this paper, we discuss insights into Vector API, which is being developed as part of OpenJDK* under Project Panama. First, we’ll go over some Vector API fundamentals, basic functionalities, and tips. We’ll then show you some code samples of vector algorithms for standard Machine Learning...

Achieving High-Performance Computing with The Intel® Distribution for Python*

Last updated: September 29, 2017Video length: 30 min

Learn how to accelerate Python* for advanced numerical, scientific, and machine learning workloads utilizing the Intel® Distribution for Python*.

Intel® Accelerates Hardware and Software Performance for Server-Side Java* Applications

Intel® contributes significantly to both software and hardware optimizations for Java*. These optimizations can deliver performance advantages for Java applications that run using the optimized Java Virtual Machine (JVM), and which are powered by Intel® Xeon® processors and Intel® Xeon Phi™...

Lab7 Systems Helps Manage an Ocean of Information

Finding efficient ways to manage the massive amounts of data generated by new technologies is a key concern for many industries. It’s especially challenging in the world of life sciences, where research breakthroughs are based on an ever-expanding ocean of information. With help from Intel and...

Quick Start Guide for the Intel® Xeon Phi™ Processor x200 Product Family

Introduction This document describes the process for taking the Intel® Xeon Phi™ processor from the point where the hardware has been received up to the point where the processor is ready to be used by the programmer. This document does: Provide a high level overview of the architecture of the...

Vector API Developer Program for Java* Software

This article introduces Vector API to Java* developers. It shows how to start using the API in Java programs, and provides examples of vector algorithms. It provides step-by-step details on how to build the Vector API and build Java applications using it. It provides the location for downloadable...

Using Intel® Math Kernel Library Compiler Assisted Offload in Intel® Xeon Phi™ Processor

Introduction Beside native execution, another usage model of using the Intel® Math Kernel Library (Intel® MKL) on an Intel® Xeon Phi™ processor is the compiler assisted offload (CAO). The CAO usage model allows users to offload Intel MKL functions and data to an Intel Xeon Phi processor by using...

Improving Performance of Math Functions with Intel® Math Kernel Library

Introduction Intel® Math Kernel Library1 (Intel® MKL) is a product that accelerates math processing routines to increase the performance of an application when running on systems equipped with Intel® processors. Intel MKL includes linear algebra, fast Fourier transforms (FFT), vector math, and...

Intel® HPC Developer Conference: For the HPC Practitioner

Published on September 18, 2017

Time to sign up for the Intel HPC Developer Conference Nov 11-12 in Denver, Colorado

Applications for Latency

The Best of Modern Code | September

Find out who is speaking at the HPC Developer Conference, do some fast computations, and a little deep learning this month.

Intel® Xeon® Processor Scalable Family Technical Overview

The new generation, the Intel® Xeon® processor Scalable family (formerly code-named Skylake-SP), is based on 14nm process technology, with many new and enhanced architecture changes including, Skylake Mesh Architecture and Intel® Advanced Vector Extensions 512 (Intel® AVX-512).

Modernizing Software with Future-Proof Code Optimizations

by Henry A. Gabb, Sr. Principal Engineer, Intel Software and Services Group Create High Performance, Scalable and Portable Parallel Code with New Intel® Parallel Studio XE 2018 Intel® Parallel Studio XE is our flagship product for software development, debugging, and tuning on Intel processor...

Intel® Xeon® Processor Scalable Family

Last updated: September 13, 2017Video length: 4 min

New micro architecture and technical features of the Intel® Xeon® Scalable Processor Family.